A single-chip SC line equalizer system for full duplex multi-bit rate digital transmission

Abstract

This paper presents a single-chip SC line equalizer system, which can be applied to full duplex digital transmission. Adaptive SC filters, constructed with programmable capacitor arrays (PCAs), usually cause undesired responses, such as spike noise and transient response, which degrade data transmission quality. In order to avoid these phenomena, a duplex SC equalizer is introduced, which has the same circuits in parallel. PCAs in one duplex equalizer, whose output is not transfered, are varied. After the undesired phenomena vanish, the output is alternated. The equalizer system can be applied to several different bit rates,merely by changing the external control signals. An algorithm for a bridged tap echo canceller is modified for a more general case. A DC offset canceller and an auto zero circuit are employed for variable and fixed blocks, respectively. A line equalizer system was designed for four different bit rates, ranging from 3.2 to 64 kbps, and an LSI was fabricated using a 3Dm CMOS process. Chip area is 45.5 mm2, and power dissipation is 190 mW with a single +5V power supply.