A simplified hybrid carrier‐based PWM technique for three‐level NPC inverters considering neutral‐point voltage balance

Abstract

An in‐depth analysis and comparison between the virtual space vector pulse width modulation (VSVPWM) method and the space vector pulse width modulation (SVPWM) method is presented in this paper. Compared to SVPWM, VSVPWM can achieve the balance of the neutral‐point voltage for any load over the full range of the inverter output voltage and for all load power factors. Nevertheless, VSVPWM would cause higher dv/dt of output voltages, higher voltage total harmonic distortion, and slower voltage‐balancing dynamic. A detailed analysis on these drawbacks is given. Then, the relationship between the neutral‐point current and the factor k0, which is employed to adjust the ratio of time of application of small vectors in a pair, is studied comprehensively, and a modified zero‐sequence voltage injection method for the two‐level inverter is introduced into the small hexagons of the three‐level space vector diagram. A simplified hybrid carrier‐based pulse width modulation (PWM) method is developed. Compared to VSVPWM, the proposed PWM method is not only easy to implement voltage‐balancing control but also reduces the switching frequencies of the devices and achieves better output voltage spectra and faster voltage‐balancing dynamic. All these benefits of the proposed method are verified through experimentation. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A Simplified Virtual Vector PWM Algorithm to Balance the Capacitor Voltages of Four-Level Diode-Clamped Converter

“…So, the voltage balancing process of the top and bottom capacitors becomes similar to three-level NPC converter. The capacitor voltage balancing of three-level NPC converter has been discussed in many papers in literature [16,32,54,55]. The relation between the neutral point currents and voltage ripple caused by the NP currents in top and bottom capacitors can be derived from (5) and expressed as:…”

“…where dVS1 is the duty ratio of the small vector and k [0, 1] is sharing factor between two redundant switching states. The calculation of the sharing factor k is similar to 3L-DCC which has been discussed in detail in [32]. Considering the positive direction of phase current (ix > 0), if (VC3 > VC1) switching state "3VV" is used to decrease the top capacitor voltage and increase the bottom capacitor voltage and vice versa for the reverse direction of current.…”

“…A carrier-based equivalent PWM method is presented in [30,31] to reduce the computation burden and simple implementation. VVPWM technique can attain the capacitor voltage balancing of three level inverter for all operational conditions but it faces few problems such as higher switching frequency of the devices that increases the switching losses, higher dv/dt and increase in THD as compared conventional SVPWM (CSVPWM) [32]. Some hybrid PWM techniques have been presented in [32][33][34] to sum up the advantages of SVPWM and VVPWM techniques.…”

“…VVPWM technique can attain the capacitor voltage balancing of three level inverter for all operational conditions but it faces few problems such as higher switching frequency of the devices that increases the switching losses, higher dv/dt and increase in THD as compared conventional SVPWM (CSVPWM) [32]. Some hybrid PWM techniques have been presented in [32][33][34] to sum up the advantages of SVPWM and VVPWM techniques. However, it is very hard to balance the capacitor voltages of the inverters with more than three levels.…”