A simple RISC microprocessor core designed for digital set-top-box applications

A true 16-bit RISC processor has been designed 16/ 16 using VHDL. Hierarchical approach has been used so that basic Data Lines OutDut Port units can be modeled using behavioral programming. These basic 16 16 units are combined using structural programming. Four stage AddressLine Input Port (viz. instruction fetch stage, instruction decode stage, execution stage and memory/lO-writeback stage) pipelining is used to Processor Read

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FPGA Implementation of a 64-Bit RISC Processor Using VHDL

Imran¹,

Ramananjaneyulu²

2012

IJRES

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In this paper, the Field Programmable Gate Array (FPGA) based 64-bit RISC processor with built-in-self test (BIST) feature implemented using VHDL and was, in turn, verified on Xilinx ISE simulator. The VHDL code supports FPGA, System-On-Chip (SOC), and Spartan 3E kit. This paper also presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte’s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits, smart phones, ATMs.<em> </em>

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A simple RISC microprocessor core designed for digital set-top-box applications

Cited by 3 publications

References 8 publications

Design support systems: A case study of modular design of the set-top box from design knowledge externalization perspective

Design support systems: A case study of modular design of the set-top box from design knowledge externalization perspective

Implementation of RISC Processor on FPGA

FPGA Implementation of a 64-Bit RISC Processor Using VHDL

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