A simple procedure for fabricating molecular-sized gap junctions using conventional photolithography

Naitoh, Yasuhisa; Horikawa, Masayo; Yatabe, Tetsuo; Funaki, Takashi; Abe, Hidekazu; Liang, Tien-Tzu; Suzuki, Yoshishige; Shimizu, Tetsuo; Kawanishi, Yuji; Mizutani, Wataru

doi:10.1088/0957-4484/17/9/056

Cited by 6 publications

(9 citation statements)

References 18 publications

(28 reference statements)

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“…For example, palladium wires may be grown between two photolithographically defined palladium electrodes as demonstrated by Cheng et al, resulting in single nanowires in well defined locations 4 . Another approach that yields single nanowires in precise locations is electrochemical growth or evaporation 5 along the sidewall of a photoresist pattern. Some assembly attempts include chemical patterning of a substrate to selectively promote/discourage adhesion 6 , contacting individual wires with precisely placed electrodes using a focused ion/electron beam deposition technique 7 , and generating dielectrophoretic forces on nanowires in solution 8,9 .…”

Section: Use As Transfer Printed Electrodesmentioning

confidence: 99%

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Nano Electronic Materials

2017

Jpn. J. Appl. Phys.

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This thesis explores fabrication methods and characterization of novel materials used in field effect transistors, including metallic nanowires, carbon nanotubes, and graphene.Networks of conductive nanotubes are promising candidates for thin film electrode alternatives due to their desirable transparency, flexibility, and potential for large-scale processing. Silver nanowire and carbon nanotube networks are evaluated for their use as thin film electrode alternatives. Growth of silver nanowires in porous alumina membranes, dispersion onto a variety of substrates, and patterning is described. Metallic carbon nanotubes are suspended in aqueous solutions, airbrushed onto substrates, and patterned. The conductivity and transparency of both networks is evaluated against industry standards.Graphene is a two dimensional gapless semimetal that demonstrates outstanding room temperature mobilities, optical transparency, mechanical strength, and sustains large current densities, all desirable properties for semiconductors used in field effect transistors. Graphene's low on/off ratio and low throughput fabrication techniques have yet to be overcome before it becomes commercially viable.Silicon oxide substrates are common dielectrics in field effect transistors and instrumental in locating mechanically exfoliated graphene. The morphology of two different silicon oxides have been studied statistically with atomic force microscopy and scaling analysis. Tailoring the physical properties of these substrates may provide a control of graphene's electrical properties.A silicon oxide substrate may also be chemically altered to control the properties of graphene. I have modified silicon oxide with self-assembled monolayers with various terminal groups to control the field near the graphene. I characterize the monolayers with atomic force microscopy, x-ray photospectroscopy, and contact angles. I characterize graphene on these substrates using Raman microscopy and transport measurements.Finally, I examine low frequency noise in graphene field effect transistors on conventional silicon oxide substrates. As devices become smaller, the signal to noise ratio of these devices becomes important. Low frequency noise occurs on long time scales and must be controlled for device stability. I measure novel behavior of low frequency noise in multiple graphene devices. The noise may be described electronhole puddles in the graphene that are caused by trapped charges near the surface of silicon oxide. NANOELECTRONIC MATERIALS

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Section: Use As Transfer Printed Electrodesmentioning

confidence: 99%

“…4 Scaling parameters for both oxides with different AFM tips.. 57 Table 3. 5 Scaling parameters and Fourier amplitudes for both oxides… 62 Table 5.1 Surface free energy components for test liquids……………. 83 Table 5.…”

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confidence: 99%

Nano Electronic Materials

2017

Jpn. J. Appl. Phys.

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“…Most of the above investigations involved nanoscale structures fabricated by electron-beam lithography (EBL). However, because EBL is expensive and time-consuming, a procedure that does not require the use of EBL is preferred for industrialization [7].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Nanoimprinting Multilayer Lift-off Process using Spin-on-glass for Nanogap Electrode Array

Hashiguchi

Suzuki

Hiroshima

et al. 2018

J. Photopol. Sci. Technol.

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Nanogap electrodes are expected to aid in the study of the electrical properties of single molecules and nanoparticles, and have also been applied to non-volatile memory. However, an electrode that exhibits a large area and good reproducibility is yet to be found. We investigate the nanogap fabrication method combining UV nanoimprint lithography and electromigration. A three-layer lift-off process, using spin-on-glass as an intermediate layer with high etching selectivity, is evaluated. Nanowire array patterns are fabricated in a 9-mm square in the process, which demonstrate the nanogap characteristics of resistance switching effects.

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“…Such small islands are very difficult to fabricate even though conventional electron beam lithography technique is used. In this paper, we fabricated a SHT using nanometer-sized gap junctions by shadow evaporation method [4], and they showed room temperature SHT behaviors.…”

Section: Introductionmentioning

confidence: 99%