A simple power-aware scheduling for multicore systems when running real-time applications

Bautista, Diana M.; Sahuquillo, Julio; Hassan, Houcine; Petit, Salvador; Duato, J.

doi:10.1109/ipdps.2008.4536220

Cited by 45 publications

(28 citation statements)

References 23 publications

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“…Optimizations for power management have traditionally focused on dynamic voltage and frequency scaling (DVFS) by operating systems [8,5]. Compiler optimizations to enhance power efficiency of applications have mostly focused on varying instruction scheduling schemes [13,16,22,26] and thread-allocation and scheduling strategies [2,1,23]. Power consumption has been estimated using architectural simulation [4,16,2], offline profiling [6], and real time monitoring of hardware counters [23,18].…”

Section: Related Workmentioning

confidence: 99%

Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Rahman

Guo

Bhat

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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This paper studies the overall system power variations of two multi-core architectures, an 8-core Intel and a 32-core AMD workstation, while using these machines to execute a wide variety of sequential and multi-threaded benchmarks using varying compiler optimization settings and runtime configurations. Our extensive experimental study provides insights for answering two questions: 1) what degrees of impact can application level optimizations have on reducing the overall system power consumption of modern CMP architectures; and 2) what strategies can compilers and application developers adopt to achieve a balanced performance and power efficiency for applications from a variety of science and embedded systems domains.

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Section: Related Workmentioning

confidence: 99%

Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Rahman

Guo

Bhat

et al. 2012

Proceedings of the 9th Conference on Computing Frontiers

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show abstract

“…In studies such as [6][7][8][9][10][11][12] efforts have been devoted to model or estimate the power usage of individual applications or workloads. These studies monitor the use of system's component (in particular the processor and memory) during the workload execution via hardware performance counters and correlate them with the power consumed by the system when running that workload to derive a power model.…”

Section: Power/energy Estimation Using Hardware Performance Countersmentioning

confidence: 99%

Exploiting performance counters to predict and improve energy performance of HPC systems

Chetsa

Lefèvre

Pierson

et al. 2014

Future Generation Computer Systems

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International audienceHardware monitoring through performance counters is available on almost all modern processors. Although these counters are originally designed for performance tuning, they have also been used for evaluating power consumption. We propose two approaches for modelling and understanding the behaviour of high performance computing (HPC) systems relying on hardware monitoring counters. We evaluate the effectiveness of our system modelling approach considering both optimizing the energy usage of HPC systems and predicting HPC applications’ energy consumption as target objectives. Although hardware monitoring counters are used for modelling the system, other methods–including partial phase recognition and cross platform energy prediction–are used for energy optimization and prediction. Experimental results for energy prediction demonstrate that we can accurately predict the peak energy consumption of an application on a target platform; whereas, results for energy optimization indicate that with no a priori knowledge of workloads sharing the platform we can save up to 24% of the overall HPC system’s energy consumption under benchmarks and real-life workloads

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“…A more complete definition presents an application's energy profile as its part of the energy footprint variation of the overall system during its execution. In studies such as [5,11,4,16,3,10,18] efforts have been devoted to model power usage of system components (CPU, memory, disk, network) via hardware performance counters or hardware monitoring events. From those studies, the energy profile of an application can also be defined as a set of measurements (hardware monitoring events collected per-process or system-wide) over a time interval T such that there exists a combination of them estimating the power/energy used by the application or the whole system over T. The last definition describes the energy consumed by the application or the whole system via a set of hardware monitoring counters.…”

Section: System Model Use-casesmentioning

confidence: 99%

DNA-Inspired Scheme for Building the Energy Profile of HPC Systems

Chetsa

Lefèvre

Pierson³

et al. 2012

Energy Efficient Data Centers

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Abstract. Energy usage is becoming a challenge for the design of next generation large scale distributed systems. This paper explores an innovative approach of profiling such systems. It proposes a DNA-like solution without making any assumptions on the running applications and used hardware. This profiling based on internal counters usage and energy monitoring allows to isolate specific phases during the execution and enables some energy consumption control and energy usage prediction. First experimental validations of the system modeling are presented and analyzed.

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A simple power-aware scheduling for multicore systems when running real-time applications

Abstract: High-performance microprocessors, e.g., multithreaded and multicore processors, are

Cited by 45 publications

References 23 publications

Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Studying the impact of application-level optimizations on the power consumption of multi-core architectures

Exploiting performance counters to predict and improve energy performance of HPC systems

DNA-Inspired Scheme for Building the Energy Profile of HPC Systems

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