A Simple Miller Compensation With Essential Bandwidth Improvement

Algueta-Miguel, José M.; Ramírez-Angulo, J.; Mirazo, Enrique; Lopez-Martin, A.J.; Carvajal, R.G.

doi:10.1109/tvlsi.2017.2733082

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…However, the architecture of a multistage operational amplifier always results in the closed‐loop instability on account of the increased number of high‐resistance nodes. To solve the instability issue, various frequency compensation techniques have been studied [ 6 – 29 ] .…”

Section: Introductionmentioning

confidence: 99%

“…For the Simple Miller compensation (SMC) framework, only one compensation capacitor is required. Hence, a better compensation result can be realized, and the chip area can be also greatly reduced [13,14] . Damping factor control frequency compensation (DFCFC) adds a damping factor control block to control the damping factor and make the amplifier stable, which is suited to large load capacitance [15] .…”

Section: Introductionmentioning

confidence: 99%

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A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

Liang

Zirui

Liu

et al. 2021

Chinese J of Electronics

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A four‐stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed‐forward Gm‐stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two‐stage amplifier linked with a three‐stage amplifier can realize a five‐stage amplifier, two three‐stage amplifiers linked can realize a six‐stage amplifier. A four‐stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed‐forward transconductance stage, and the second part is the two‐segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small‐signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2‐pF load capacitance, a direct current gain of 109dB and a gain‐bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8‐V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

Liang

Zirui

Liu

et al. 2021

Chinese J of Electronics

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A High Gain, High BW OP AMP with Frequency Compensation Techniques at 65 nm Technology

Sama

Sarma

2021

Wseas Transactions on Electronics

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OP-AMPs finds applications in different domains of electronics engineering including communications. There has been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier which uses frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain band width product (GBWP), Phase Margin and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain with a phase margin of 60o.

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Miller’s Compensation Techniques for a High Gain, High BW OP-AMP at 65 nm Technology

Sama

Sarma

2022

International Journal of Circuits, Systems and Signal Processing

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OP-AMPs find applications in different domains of electronics engineering including communications. There have been several OP-AMP configurations realized in the last decades for different target applications. But with the evolution of communication standards, to meet the demand for high data rate over the years, the requirement for a high frequency and high BW OP-AMP is gaining attention. This makes the design challenge much higher. This paper presents a two-stage CMOS amplifier that uses a frequency compensation method to facilitate higher BW. Different parameters like Gain, Gain bandwidth product (GBWP), Phase Margin, and Total Power dissipation are considered in this design. A step-by-step procedure for an efficient amplifier design is followed using frequency compensation. We have achieved a gain-bandwidth product (GBWP) of 110 MHz that is capable of driving large capacitive loads. It also achieves 77.7 dB gain and phase margin of 60° with the minimal noise of 2.27 μ^V/√ Hz and the slew rate of 20.12 V/ms

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A Simple Miller Compensation With Essential Bandwidth Improvement

Cited by 3 publications

References 10 publications

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique

A High Gain, High BW OP AMP with Frequency Compensation Techniques at 65 nm Technology

Miller’s Compensation Techniques for a High Gain, High BW OP-AMP at 65 nm Technology

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