A Simple Heterogeneous Redundant Design Method for Finite State Machines on FPGAs

Itagawa, Takanori; Kamasaka, Ryo; Shibata, Yuichiro

doi:10.1007/978-3-030-22354-0_40

Cited by 2 publications

(4 citation statements)

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“…For the duplex redundant design, a large number of errors were overlooked in the homogeneous redundant designs DSP-DSP and LUT-LUT. This 5a) is almost consistent with the evaluation results for simple circuits described in RTL [2,13]. We also evaluated homogeneous TMR, which is commonly used for today's practical systems.…”

Section: Resultssupporting

confidence: 86%

“…The difference is presumed to be caused by the common cause fault on this state machine in an overclocking environment. For the state machines, it has been suggested that diversification by encoding can increase the effectiveness of heterogeneous redundancy [13]. The default state encoding by Vivado HLS is 'one-hot,' and it does not have diversity with respect to the encoding of the redundant designs implemented in this work.…”

Section: Resultsmentioning

confidence: 99%

“…A design flow of FPGA circuits consists of logic synthesis of design description, technology mapping, place and route, and generation of configuration data. The authors of [1,2,13] have proposed a heterogeneous redundant design method focusing on the diversity in the technology mapping process. In the technology mapping process, in which FPGA resources are assigned to the netlist generated by logic synthesis, the diversity can be introduced depending on a design strategy.…”

Section: Methodsmentioning

confidence: 99%

“…We have proposed a method to diversify the modules on FPGA circuits by only inserting simple directives into the RTL code [1,2,13]. It has been shown that the method can improve reliability against common cause fault while reducing design cost.…”

Section: Related Workmentioning

confidence: 99%

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Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs

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Miyata

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IJNC

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Field programmable gate arrays (FPGAs) are now used in a wide range of application fields including aerospace, medical, and industrial infrastructure systems, where not only soft errors but also common cause faults must be treated in systems design. Although the heterogeneous redundant design is preferable in such application fields, it tends to be a large burden on system designers. Even with high-level synthesis (HLS) technologies, which have enabled productive design processes without register transfer level (RTL) descriptions, an efficient design approach for redundant design is not always clear. In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach focuses on diversity in FPGA technology mapping. For example, two different implementations for a multiplier, one with look-up tables (LUTs) and the other with digital signal processing (DSP) blocks, can form heterogeneous redundancy. The strategylevel approach makes the use of the optimization options offered by an FPGA design tool, called strategies, as a source of diversity. For example, two different implementations can be derived from the same hardware description with area oriented optimization and performance oriented optimization. With both approaches, heterogeneous implementation variants can be generated from the same hardware description code. For evaluation, we implemented homogeneous and heterogeneous redundant designs for proportional-integralderivative (PID) control with those approaches and evaluated their error detection capability and reliability with overclock simulation. The resource-level approach showed that heterogeneous redundant designs by the proposed method have a high error detection rate in both RTL and HLS implementations in an application-level circuit. Although the detection rate of the strategy-level approach was not as high as that of the resource-level one, it was shown to have a certain diversification effect.

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Section: Resultssupporting

confidence: 86%

Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations