2010 IEEE International Reliability Physics Symposium 2010
DOI: 10.1109/irps.2010.5488771
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A simple electrical method for etch bias and process reliability determination

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Cited by 12 publications
(8 citation statements)
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“…By using ¼ 0:71, the other parameters can be estimated by the multiple linear regression analysis using Eq. (8). As shown in Fig.…”
Section: Analysis Of Electric Field Dependence Datamentioning
confidence: 82%
“…By using ¼ 0:71, the other parameters can be estimated by the multiple linear regression analysis using Eq. (8). As shown in Fig.…”
Section: Analysis Of Electric Field Dependence Datamentioning
confidence: 82%
“…In advanced semiconductor technologies, the impact of process variations such as line-edge roughness in etching processes, deviation in lithography alignment, variations in Via and contact diameter, and unevenness in film thickness between the wiring/gate and Via have large effects on lifetime variations. 21,[34][35][36][37][38][39] Because of these fluctuations, the observed lifetime distribution of the TDDB does not follow the commonly used Weibull distribution approach. In this case, the probability plot shows a convex upward shape.…”
Section: Break Of the Uniformity Assumptionmentioning
confidence: 99%
“…This situation may change somewhat, however, if metal trench capping approaches are used, but without a secondary dielectric capping layer. (5) Vias tend to form distended regions around the top of the via at the trench/capping layer interface that arise from taper effects and via misalignment [242]. (4) Line terminations [239,240] and turns within interconnect layouts have particularly high local fields due to electric field enhancement at corners [26,27,241].…”
Section: Interconnect Layout and Test Structuresmentioning
confidence: 99%