A SiGe BiCMOS 1ns fast hopping frequency synthesizer for UWB radio

Leenaerts, D.M.W.; Beek, C.Z. van de; Weide, G. van der; Bergervoet, J.; Harish, K.S.; Waite, H.; Zhang, Y.; Razzell, C.; Roovers, R.

doi:10.1109/isscc.2005.1493939

Cited by 50 publications

(48 citation statements)

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“…The first PLL generates the center frequency of the middle sub-band while the second one produces the channel-spacing frequency of 528 MHz. The SSB mixers take the output frequencies of the two PLLs to generate the required center frequency of the other two sub-bands through upconversion and downconversion operations [19]- [23]. The advantage of employing this architecture is that the band hopping speed is independent of the settling time of the PLLs.…”

Section: Plls and Single-sideband Mixersmentioning

confidence: 99%

“…The nonlinearity of the SSB mixers generates spurious tones close to the frequency of the coexisting wireless standard which downconvert the out-of-band interferers into the desired UWB band and corrupt the signal, as discussed in Section 3.2.2. This implies that notch filters are required for out-of-band suppression as explained in [19]. Moreover, the die area will be increased due the use of inductors in the two VCOs and/or the SSB mixers [11].…”

Section: Plls and Single-sideband Mixersmentioning

confidence: 99%

“…To reduce the effect of charge sharing due to the switching activities on the loop control voltage, a common-source buffer (M 16 -M 19 ) is added to the delay element as shown in Figure 8.12. It has been observed that the charge sharing phenomenon is in fact the main limiting factor in achieving very accurate compensations, as it modulates the control voltage.…”

Section: Variable-gain Delay Elementmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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Section: Plls and Single-sideband Mixersmentioning

confidence: 99%

Section: Plls and Single-sideband Mixersmentioning

confidence: 99%

Section: Variable-gain Delay Elementmentioning

confidence: 99%

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Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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“…A state-of-the art implementation of a synthesizer for MBOA UWB, meeting all above stated requirements, is presented in [4] and [5]. This architecture is based on two PLLs and a single single-sideband (SSB) mixer.…”

Section: Introductionmentioning

confidence: 99%

“…However, due to the need for two SSB-mixers and several frequency dividers, spurious tones are an issue. Both [5] and [7] use a SiGe BiCMOS process to achieve optimal performance. In [8], a CMOS implementation is discussed where the synthesizer is based on a straightforward 3-PLL implementation using ring oscillators.…”

Section: Introductionmentioning

confidence: 99%