A SiGe 8–18-GHz Receiver With Built-In-Testing Capability for Self-Healing Applications

Howard, Duane C.; Saha, Prabir; Shankar, Subramaniam; England, Troy; Cardoso, Adilson S.; Diestelhorst, R.M.; Jung, Seungmin; Cressler, John D.

doi:10.1109/tmtt.2014.2345334

Cited by 11 publications

(17 citation statements)

References 17 publications

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“…In order to simplify the analysis, the single-ended output is considered instead of . By referring the input power to an impedance of 50 , i.e., , the transfer function of the amplitude detector and TIA can be expressed as (9) Based on circuit simulation, since the op amp is compensated by a miller capacitor, where the second pole is 6.45 times higher than the unit gain frequency, it can be simply modeled as a single-pole transfer function as (10) By substituting (10) into (9), the circuit is inherently a two-pole system given as (11) Under the assumption of and , the denominator can be expressed in the form of , and the natural frequency and the damping ratio are (12) and (13) respectively. Based on the feedback control theory, the settling time within 2% error is approximated as [21] …”

Section: Amplitude Detector and Transimpedance Amplifiermentioning

confidence: 99%

“…In order to alleviate such limitations, efforts have been made to develop built-in self-test (BIST) and calibration techniques for RF amplifiers over the past decade [1]- [12].…”

Section: Introductionmentioning

confidence: 99%

“…In the succeeding stage of the research stream, the concept of self-healing has been proposed, where the built-in functions are advanced from simply testing to a complete gain calibration procedure [7]- [12]. Based on the previous gain extraction concept in [4], a fully-integrated closed-loop system is presented in [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Analog On-Line Gain Calibration Loop for RF Amplifiers

Hsieh

et al. 2015

IEEE Trans. Circuits Syst. I

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This paper presents an analog on-line gain calibration loop for radio-frequency (RF) amplifiers. In the proposed calibration scheme, the gain of an RF amplifier is determined by programmable resistor ratios of two transimpedance amplifiers (TIAs), while the corresponding control voltage is generated through a differential difference amplifier (DDA). Being the first work to propose a continuous-time gain calibration technique for RF amplifiers, the loop dynamics such as settling time, stability and control voltage ripples are analyzed by means of mathematical modeling of each circuit building block. As a result, a systematic design procedure is developed. In order to validate the concept, a 5.2-GHz variable-gain low-noise amplifier (LNA) is integrated with the proposed analog gain calibration loop for demonstration. By using a standard 0.18-CMOS process, the fabricated circuit consumes a total dc power of 18.5 mW from a 1.8-V supply, while the measured maximum gain error is less than 1 dB. Index Terms-Amplitude detectors, built-in self-test (BIST), gain calibration, loop stability, RF amplifiers, transimpedance amplifiers (TIAs). 1549-8328

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Section: Amplitude Detector and Transimpedance Amplifiermentioning

confidence: 99%

“…In order to alleviate such limitations, efforts have been made to develop built-in self-test (BIST) and calibration techniques for RF amplifiers over the past decade [1]- [12].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An Analog On-Line Gain Calibration Loop for RF Amplifiers

Hsieh

et al. 2015

IEEE Trans. Circuits Syst. I

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“…To reduce the costs of testing RF integrated circuits (ICs) with commercial vector network analyzers (VNAs), implementing on-chip S-parameter measurement is one promising research direction [3][4][5][6][7][8][9][10]. Jayaraman [3], Goyal [4], Wu [5], and Howard [6] demonstrated how to exploit the concept of the on-chip measurement to perform self-healing adjustments on RF circuits. Nehring [7] and Niitsu [8] illustrated the possibilities of applying the embedded S-parameter measurement to the field of biomedicine.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, the additional resistance and phase lag between Ports 1 and 3 can be expressed as Eqs. (5) and (6), where 1.96Ω and 20 degrees are replaced by 1.9588Ω and 20.57 degrees to enhance the precision of numerical computation. Since linear algebra [34] requires two independent equations to solve two variables, x and y can be derived by solving the simultaneous Eqs.…”

mentioning

confidence: 99%

A Novel Investigation Method for the S21 Detection Circuit

Lee

2020

Int. j. eng. technol. innov.

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This research proposes a novel method to investigate the performance of the S21 detection circuit. Aiming at low frequencies or DC, the method serves as an efficient way of verification and enjoys the benefit of low testing costs. The novel investigation method is demonstrated at 50 MHz and verified by the scattering parameters at 11.05 GHz. Based on the investigation, a model of process variations is constructed. The length of the interface paths is estimated by the model to be 63µm, which is consistent with the corresponding length of 74.6µm in the layout. For the measured phase and magnitude, the model indicates that the process variations in the device under test cause errors of 18.91% and 1.27%, whereas those in the interface paths lead to errors of 1.83% and 1%. Based on the model, practical recommendations are also proposed to further improve the measurement precision in the future.

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An Integrated Detection Circuit for Transmission Coefficients

Lee

Huang

2020

IEEE Access

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As the applications of radio-frequency (RF) circuits continue to prosper, scattering parameters (S-parameters) play an essential role in the verification of a variety of chips. The traditional way to measure the S-parameters of RF integrated circuits (RFICs) is by using vector network analyzers (VNA). However, measuring RFICs with VNAs is very expensive and likely to reduce the profits of IC products. An implementation of the embedded circuit for S-parameter measurement can greatly reduce the costs of using expensive VNAs. Another reason to embed the circuit for S-parameter measurement is to increase the portion of a chip that can be measured. Besides, novel technologies, such as three-dimensional ICs, will require advanced methods for on-chip verifications of RF circuits since many RF nodes may be buried deep inside a chip stack. In view of these needs, this paper proposes a simple network that can realize onchip S 21 measurements. The greatest advantages of this circuit are the easy implementation and technology independence. To verify the feasibility of the circuit, we fabricated the test chips by using the 0.18-µm IBM 7RF process. The measurement results show the expected behavior and demonstrate the feasibility of the design concept. INDEX TERMS Radio frequency (RF), S-parameters, integrated circuit (IC), vector network analyzer (VNA), automatic test equipment (ATE), divider (DIV), device under test (DUT), embedded testing, bandwidth, calibration.

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A SiGe 8–18-GHz Receiver With Built-In-Testing Capability for Self-Healing Applications

Cited by 11 publications

References 17 publications

An Analog On-Line Gain Calibration Loop for RF Amplifiers

An Analog On-Line Gain Calibration Loop for RF Amplifiers

A Novel Investigation Method for the S21 Detection Circuit

An Integrated Detection Circuit for Transmission Coefficients

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