A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators

Lin, Yan; Hsu, Shawn S. H.

doi:10.1109/jssc.2017.2732730

IEEE J. Solid-State Circuits

2017

DOI: 10.1109/jssc.2017.2732730

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A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators

Yan Lin

Shawn S. H. Hsu

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Cited by 2 publications

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“…At frequency offsets far from the carrier or equivalently over small timescales, the improvement in frequency stability is less than ∝ 1/ √ p. This is due to the finite time associated with correction of noise perturbations in a weakly coupled system [13]. However, the possibility of achieving multiple clock phases with resolutions independent of the smallest gate delay for a given technology [11] and ease of low-skew lowjitter timing distribution [14] make their use viable for a variety of applications [15]- [18]. This article presents collective pulse oscillators (CPOs) that are realized using pulse regenerative amplifiers [19] as the main delay element.…”

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confidence: 99%

Design and Analysis of Collective Pulse Oscillators

Mukim

Dalakoti

McCarthy

et al. 2020

IEEE Trans. VLSI Syst.

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Collective pulse oscillators (CPOs) are novel designs constructed using pulse regenerative amplifiers that exhibit timevariant gate delay based on the residual charge from past state. This property makes it possible to achieve precise phase resolutions smaller than a pulse gate delay and/or provide identical phase taps at multiple physical locations. CPOs exhibit temporal phase error correction that results in an improvement in frequency stability ∝ −10 log p for power ∝ p across all timescales beyond the correction settling time. While CPOs result in device noise-based figure of merits (FoMs) comparable to that of ring oscillators, they are more resilient to power-coupled and impulse noise. This article presents a systematic time-domain analysis of the properties of CPOs based on an abstract model that captures the time-variant delay of pulse gates. Closedform analytic solutions for CPOs disturbed by impulse noise are derived, and higher order CPOs with continuous noise injection are analyzed using behavioral simulations and characterized using Allan deviation. Hspice simulation results are presented to validate the model and compare CPOs with ring oscillators. Allan deviation and phase noise measurements on CPOs of 8 and 40 gates fabricated in GFUS8RF (130-nm) technology corroborate the theory and simulation results.

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mentioning

confidence: 99%

Design and Analysis of Collective Pulse Oscillators

Mukim

Dalakoti

McCarthy

et al. 2020

IEEE Trans. VLSI Syst.

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Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

Yang,

Chen,

Cheng

et al. 2024

Circuit Theory & Apps

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In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.

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A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators

Cited by 2 publications

References 39 publications

Design and Analysis of Collective Pulse Oscillators

Design and Analysis of Collective Pulse Oscillators

Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

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