A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

Pottbacker, A.; Langmann, U.; Schreiber, Horst

doi:10.1109/4.173101

Cited by 117 publications

(48 citation statements)

References 5 publications

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“…From this figure, it can be found that the full-rate PD is actually a double-edge-triggered flip-flop (DETFF), which consists of two latches and a conventional selector shown in Fig. 10(a) and (b), and the PFD [38] is composed of two identical DETFFs (or PDs) and a tri-state DETFF (Tri-DETFF) which is also called a frequency detector (FD). The main difference of the Tri-DETFF from the DETFF is that a tri-state selector shown in Fig.…”

Section: Circuit Design For Interface Imentioning

confidence: 99%

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Zhang¹,

Li²,

Wang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Two novel clocking strategies for a highspeed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18 µm CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

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Section: Circuit Design For Interface Imentioning

confidence: 99%

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Zhang¹,

Li²,

Wang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…To cover the wide range of data rates of the clock and data recovery (CDR) loops and to compensate for the process, voltage, and temperature (PVT) variations of clock frequency from voltage controlled oscillator (VCO), various frequency acquisition techniques have been utilized [1][2][3][4][5][6][7][8][9] in the serial data interfaces. However, most of these techniques originate from the thought that the phase detectors cannot detect the frequency difference between the received data and the recovered clock in the CDR loops.…”

Section: Introductionmentioning

confidence: 99%

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Byun¹

2018

Electronics

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Abstract:The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (f DATA ) and the recovered clock frequency (f CLK ) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of f DATA and f CLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.

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“…The PFD used, and illustrated in Figure 2, is a minor variation of one presented by Pottbiicker et al [2]. The PFD consist of two identical Phase-Detectors (PD), a Frequency-Detector (FD) and a Loop Filter Driver.…”

Section: Figure 1 Cdr Block Diagrammentioning

confidence: 99%

“…In previous work [2], the outputs from one PD and the FD are summed in the analogue domain, resulting in a ternary output from the PFD. To avoid this, and associated problems, the PFD outputs are processed digitally in the Loop Filter Driver.…”

Section: Figure 1 Cdr Block Diagrammentioning

confidence: 99%

Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

Hansen

Salama²

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

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A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s

Cited by 117 publications

References 5 publications

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Clock- and data-recovery IC with demultiplexer for a 2.5 Gb/s ATM physical layer controller

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