A set of traffic models for Network-on-Chip benchmarking

Pekkarinen, Esko; Lehtonen, Lasse; Salminen, Erno; Hämäläinen, Timo D.

doi:10.1109/issoc.2011.6089221

Cited by 17 publications

(3 citation statements)

References 9 publications

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“…In [11][23] [24], communication-centred design is proposed and key benchmark characteristics are defined. Starting from this initiative, several works propose benchmarks derived from: i) real applications traffic traces [17] [12], ii) statistical models extracted from applications [25] and iii) communication task graphs [19] [27]. Unlike the benchmarks for a conventional parallel system, they are not abundantly available and well-maintained for broader research use.…”

Section: Related Workmentioning

confidence: 99%

“…Synthetic benchmark suites are designed based on either task graphs that are statically extracted from applications (e.g., source code analysis) [19] or use stochastic models assuming a certain class of data generation processes (e.g., Poisson process) [8]. In contrast with the full-system simulations, the simulation time is greatly reduced due to simplified system details.…”

Section: Introductionmentioning

confidence: 99%

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Scalable and realistic benchmark synthesis for efficient NoC performance evaluation

Xue

Bogdan

2016

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The complexity of the design-space exploration of largescale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. Consequently, it is crucial to develop rigorous mathematical frameworks for capturing the task dependencies of varied applications to foster the generation of realistic benchmarks that can guide the NoC design. However, the current NoC benchmark suites either lack portability and poorly scale as they require intensive development efforts on specific architectures and simulation time, or are synthesized based on purely stochastic models that are disconnected with real applications, which may easily lead to biased and/or delayed design choices. To overcome these drawbacks, we propose a benchmark synthesis framework that i) not only allows extraction of dynamical task dependencies of the application and synthesize traffic workloads spatio-temporally consistent with realistic traffic behavior, ii) but can also be easily scaled by the proposed complexnetwork inspired algorithm for large benchmark generation while preserving key structural features that governs application communication behaviors. We validate the proposed framework on a large-scale simulation environment by running a set of real applications. Experimental results show that the synthesized benchmarks respect the traffic patterns of the original applications and preserve key features of application task structures.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scalable and realistic benchmark synthesis for efficient NoC performance evaluation

Xue

Bogdan

2016

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…The software model in the traffic generator is based on Kahn process networks [12]. Applications such as UMTS-modems, an H.263 compatible video encoder and decoder, or an audio-video benchmark have been implemented for the NocBench traffic simulator [13].…”

Section: Related Workmentioning

confidence: 99%

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

Joseph

Pionteck

2014

2014 International Symposium on System-on-Chip (SoC)

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This papers presents the design of a Network-on Chip (NoC) simulator for design space exploration of router ar chitectures. The simulator supports cycle-accurate router models and in addition allows the simulation of router architectures, which can adjust their processing according to the traffic type. Realistic traffic patterns are derived from task graph models of real-world applications that are simulated in parallel to the NoC at transaction level. Combining cycle-accurate router simulation and abstract task graph simulation circumvents the limitations of most NoC simulators, which either use synthetic traffic patterns or unrealistic and fixed router models. The proposed simulator architecture is presented in detail and its suitability is shown by means of a case study.

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Benchmarking Network-on-Chip (NoC) Designs

Schwaderer¹

2012

Introduction to Open Core Protocol

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A set of traffic models for Network-on-Chip benchmarking

Cited by 17 publications

References 9 publications

Scalable and realistic benchmark synthesis for efficient NoC performance evaluation

Scalable and realistic benchmark synthesis for efficient NoC performance evaluation

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

Benchmarking Network-on-Chip (NoC) Designs

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