A serial interfacing technique for built-in and external testing of embedded memories

Nadeau-Dostie, B.; Silburt, A.L.; Agarwal, V.K.

doi:10.1109/cicc.1989.56808

Cited by 20 publications

(15 citation statements)

References 5 publications

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“…To reduce the area and routing overhead of a BIST circuit, a serial interfacing test concept was reported in [12]- [14].…”

Section: A Pipelined Ram Bist Architecturementioning

confidence: 99%

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A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

Huang

2008

2008 17th Asian Test Symposium

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Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous memories. This drastically reduces the hardware overhead of the PBIST circuit. A systematic procedure for converting a march test into a pipelined march test is also proposed. Experimental results show that the area overhead of a pipelined BIST for eight homogeneous 1k×128-bit memories is only about 0.71%.

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“…To reduce the area and routing overhead of a BIST circuit, a serial interfacing test concept was reported in [12]- [14].…”

Section: A Pipelined Ram Bist Architecturementioning

confidence: 99%

“…Multiple test pattern generators can test the corresponding memories in parallel. In [12]- [14], the serial interfacing technique was proposed to test small memories. This technique can reduce the routing overhead.…”

Section: Introductionmentioning

confidence: 99%

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

Huang

2008

2008 17th Asian Test Symposium

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“…In [6], an enhanced IEEE 1500 test wrapper for single-port RAMs was proposed. Some BIST schemes extend the technique of serial test interface for RAMs [7] to reduce the area cost of the BIST circuit [8]- [10]. In [8], a fast diagnosis scheme was proposed to reduce diagnosis time and resolve the problem of serial fault masking reported in [9].…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers

Huang

2012

IEEE Trans. VLSI Syst.

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This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.Index Terms-built-in self-test (BIST), IEEE 1500, multi-port RAM, random access memory (RAM), system-on-chip (SOC).

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“…Therefore, effective e-SRAM test and repair architecture needs to minimize the associated overhead as much as possible, in terms of both silicon area and routing. The serial interfacing technique utilized in [9][10][11][12] effectively reduced the routing overhead for e-SRAM testing. However, the test/diagnosis time is increased dramatically, which is not acceptable for production test [13][14].…”

Section: Introductionmentioning

confidence: 99%