A semiconductor yields prediction using stepwise support vector machine

An, Daewoong; Ko, Hyo-Heon; Gulambar, Turghun; Kim, Jihyun; Baek, Jun-Geol; Kim, Sung-Shick

doi:10.1109/isam.2009.5376916

Cited by 19 publications

(9 citation statements)

References 8 publications

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“…An et al suggested an efficient way to distinguish high yield and low yield using a stepwise support vector machine. Measurements of the unit voltage, current, and other electrical characteristics were used for yield prediction after fab-out [19]. However, real-time prediction at the fabrication level is not possible because the input dataset is obtained after fabout.…”

Section: Related Workmentioning

confidence: 99%

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Kim

2020

IEEE Access

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In semiconductor manufacturing, maintaining a high yield and ensuring accurate yield prediction are considerably important for improving productivity, customer satisfaction, and enhancing profitability. Despite its importance and merits, achieving wafer yield prediction with high quality and accuracy is challenging. In this paper, we propose a method for wafer edge yield prediction using a combined long short-term memory (LSTM) and feed-forward neural network (FFNN) model. Unlike previous research, we focus on the edge yield because of the higher yield loss at the wafer edge. The combined LSTM-FFNN model uses a dataset divided into two types according to data characteristics. Timeseries data are used in the case of LSTM, and non-time-series data are fed into the FFNN. When preparing the time-series data, comprising data related to the equipment and chambers, data of different chambers do not overlap, thereby rendering them as independent entities. The proposed model outperforms other models in terms of all evaluation metrics. The coefficient of determination of the proposed combined LSTM-FFNN model is 34.14%, which is almost 13% higher than that of the other compared models on average.

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Section: Related Workmentioning

confidence: 99%

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Kim

2020

IEEE Access

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“…The yield is affected by a variety of internal and external factors such as open or short circuits, scratches, contamination, etc. The cleanliness of the manufacturing environment, the proficiency of workers, and the maintenance of equipment are also important factors in yield management [6].…”

Section: A Yield Prediction In Semiconductor Manufacturingmentioning

confidence: 99%

“…In general, the first two yields are considerably more important in semiconductor manufacturing, and receive relatively more attention [12]. However, the importance of the final yield has also been highlighted as the final test becomes more time consuming and costly [6].…”

Section: A Yield Prediction In Semiconductor Manufacturingmentioning

confidence: 99%

“…Such research has investigated for predicting the fraction of pass dies on a wafer or whether a wafer is defective. Most of them focused on predicting the fab and probe yields [1], [11], [13]- [16], whereas relatively few aim to predict the final yield [6], [7]. There have also been several attempts to develop a virtual metrology system to predict the key properties of a wafer that are closely related to the yield [17] or to extract knowledge that can be utilized to enhance the yield [2], [3].…”

Section: A Yield Prediction In Semiconductor Manufacturingmentioning

confidence: 99%

“…During the wafer test, defective dies with a high probability of failing the final test are filtered out, and only repairable dies proceed to the subsequent steps [5]. However, some faulty dies pass the wafer test, which then ultimately fail the final test [6], [7]. There are a variety of possible reasons to explain this.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

Kang

Cho

et al. 2015

IEEE Trans. Semicond. Manufact.

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In semiconductor manufacturing, wafer fabrication is followed by chip assembly where individual dies are assembled as a packaged chip. In between, dies are tested in terms of their electrical properties and those which fail to pass the "wafer test" are filtered out. However, some faulty dies pass the test and cause a packaged chip to fail in the final test. The inaccuracy of the wafer test leads to waste in manufacturing time and cost. In this paper, we propose to predict the result of the final test at the die-level before assembly using wafer test items and four derivations concerning wafer map features: 1) distance of the die from the wafer center; 2) previous final yield at the die position; 3) wafer test fail rate for the adjacent dies; and 4) abnormalities of the wafer map pattern. We build prediction models with these variables using a random forest algorithm. Preliminary experimental results on actual data show that the use of these derived variables improves the prediction performance with a statistical significance, thus merits further investigation. Index Terms-Die-level failure, wafer map feature, yield prediction, final test, wafer test, random forest.

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Prediction of Package Chip Quality Using Fail Bit Count Data of the Probe Test

Park

Kim

2015

Current Approaches in Applied Artificial Intelligence

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A semiconductor yields prediction using stepwise support vector machine

Cited by 19 publications

References 8 publications

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Using Wafer Map Features to Better Predict Die-Level Failures in Final Test

Prediction of Package Chip Quality Using Fail Bit Count Data of the Probe Test

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