A semi-custom design methodology and environment for implementing superconductor adiabatic quantum-flux-parametron microprocessors

Abstract

We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14-37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices

“…Before implementing MANA, we developed a semi-custom design environment [20] which features a four-phase AQFP cell library [14] in a Cadence design environment that has been augmented with scripts and external programs to do AQFPbased combinational logic synthesis [21] and component-level place and route using the genetic algorithm and left-edge channel routing [22], [28]. Place and route tools operate on adjacent logic rows and are aware of the limited driving ability of AQFP logic cells.…”

“…We applied our combinational logic synthesis along with place and route on the ID unit of the IDI stage and the data shifter unit of the EX stage. The shifter was our first example in which we showed a full demonstration from a behavioral Verilog description to a working circuit in experiments [20], [22]. In this work, the ID unit was also synthesized using a subset of an RTL description of MANA.…”

“…No bitwise g i signals are produced in this case so the logic result propagates through the adder tree unchanged. We first experimentally validated the design of the ALU and data shifter each in separate breakout chips at low frequency in [20], but in this work, we combined them together in a high-speed test chip described later. Furthermore, we integrated architectural glue logic into the ALU, such as the generation of carry (C), negative (N), and zero (Z) flags.…”

“…The fabrication process is referred to as the AIST high-speed standard process (HSTP). We also use a semi-custom AQFP design environment described in [20] which consists of a rudimentary logic synthesis framework [21], and a geneticalgorithm-based place and route tool [22]. Some of the components of MANA are variations of previously demonstrated circuits, including a 16 × 1 b register file (RF) in [23], 8−b Kogge-Stone adders in [11], [24], and a 4−b data shifter in [22].…”

“…Some of the components of MANA are variations of previously demonstrated circuits, including a 16 × 1 b register file (RF) in [23], 8−b Kogge-Stone adders in [11], [24], and a 4−b data shifter in [22]. Preliminary low-frequency demonstrations of actual MANA units have been reported for the ALU and shifter in [20].…”