A self-learning digital neural network using wafer-scale LSI

Yasunaga, Masahiro; Masuda, Naoyuki; Yagyu, Masayoshi; Asai, Masataro; Shibata, Kouichi; Ooyama, M.; Yamada, Manabu; Sakaguchi, Takashi; Hashimoto, Michiaki

doi:10.1109/4.192041

Cited by 30 publications

(9 citation statements)

References 14 publications

(17 reference statements)

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“…As we deal with scalable design, layout usually reach the technology limitations in size and consumption, therefore the risk of defaults in the silicon circuits is greater than ever. Being able to use some circuits with one or more faulty PE in it gives the possibility to reach an higher parallelism degree for a given price, it has been often applied to massively parallel architecture such as CAM [11] and neural networks [22]. Fault tolerance can be applied to 2-D architectures [15], however it is far more simple to implement in a 1-D organisation.…”

Section: -One Dimensional Netsmentioning

confidence: 99%

Communication and Performance Trade-offs in a Systolic Machine

Archambaud

Silva

Faudemay

1994

Anais Do VI Simpósio De Arquitetura De Computadores E Processamento De Alto Desempenho (SBAC-PAD 1994)

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This paper presents the trade-offs concerning lnput-Output communications at the interface of a SIMD systolic machine, and inside the machine. These problems have been raised by the accelerating board we are currently designing. We discuss about the issues involved by VLSI design: cascadability, scalability, fault tolerance, and feasibility. We present the main features of our architecture, and the performances measured with an actual application which proves that despire of the host computer slowness, the I/O bottleneck is not a penalty for the calculation acceleration.

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Section: -One Dimensional Netsmentioning

confidence: 99%

Communication and Performance Trade-offs in a Systolic Machine

Archambaud

Silva

Faudemay

1994

Anais Do VI Simpósio De Arquitetura De Computadores E Processamento De Alto Desempenho (SBAC-PAD 1994)

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“…Since Eq. (4) is the sum of the errors for the faults which are used in the BP learning algorithm, the weight to be modified for the case where the faults are injected becomes as follows.where Awi(.,,-) is the modification of the weights when the n-multiple weight fault X is injected to the n-multiple links i.From Eq (6),. the learning algorithm proposed performs the BP algorithm, injecting the multiple-value S sequentially to each link in an MNN.…”

mentioning

confidence: 99%

A fault-value injection approach for multiple-weight-fault tolerance of MNNs

Takanami

Sato

Yang

2000

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challeng

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The methods for making multi-layered neural networks(MNN) fault-tolerant by injecting intentionally the snapping of a link or a noise into links in the learning process have been studied in the literature. However, many of them considered the fault-tolerance to the snapping of links. In this paper, we consider the fault-tolerance to the weight fault, which includes the snapping of links as a special case. We take a pattern recognition problem as a typical example. To make an MNN fault-tolerant to any single or double weight faults in a certain interval or range, we inject intentionally two extreme points of a single or double fault-values in an interval or a range to the MNN during the learning. By simulation, we investigate how much MNN becomes fault-tolerant to the weight faults depending on the injected ones. The degree of faulttolerance for a n-multiple weight fault is estimated by the number of essential multiple links. An interesting result that if only two faults of the extreme points in the interval are injected, the number of the essential links becomes zcro for single faults of all the weights in the interval is obtained. This means that MNN becomes fault-tolerant to any single weight faults in the interval. Expecting that the similar result for double faults will be obtained, we inject two extreme points in two-dimensional range. As expected, the number of ?-multiple essential links has become zero in the range. This means that MNN becomes fault-tolerant to any double weight faults in the range. Finally, we analyse the internal structure of MNN by the distribution of covariance between any two inputs of a neuron in the output layer.

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“…As an integerrepresentation architecture is used in the machine [8], all output-states from 2O to 2n-1 have the same probability to be stuck. Therefore, from the above evaluation of pd = 0.06, the global-ordering state can be achieved even with %I(%)( = F] of all stuck-outputs in the above SOM condition ( N = 100, m = 1 l),-that is, only 6% of all stuck-outputs impede the global-ordering-.…”

Section: Resultsmentioning

confidence: 99%

SOM (self-organizing map) implemented by wafer scale integration-its self-organizing behavior under defects

Yasunaga

Hachiya²

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

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Self-organizing Map (SOM) implemented by Wafer Scale Integratio provide us very-high-speed and desk-top-size hardware for practical applications synergistic effect of all neurons for ordering, the SOM-WSI is expected to reac global-ordering-state permitting defective neurons in it. In this paper, we m evaluated the robustness of the SOM against defective neurons. Furthermore, e the defective SOM were carried out and the results agreed well with the theoretical ones. From these evaluations, high fault-tolerance of the present neuro-computer has been shown. The results and the criteria derived from the evaluations can be used for the SOM-WSI design in the next step.

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A self-learning digital neural network using wafer-scale LSI

Abstract: FIELD OF THE INVENTION The present invention concerns a digital hardware archi tecture for realizing neural networks. Throughout the description, reference is made to the following list of references:

Cited by 30 publications

References 14 publications

Communication and Performance Trade-offs in a Systolic Machine

Communication and Performance Trade-offs in a Systolic Machine

A fault-value injection approach for multiple-weight-fault tolerance of MNNs

SOM (self-organizing map) implemented by wafer scale integration-its self-organizing behavior under defects

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