A Self-Isolation Scheme for Integrated Circuits

Abstract

A self-isolation scheme is proposed for fabricating transistors in semiconductor integrated circuits. Such integrated circuits with double-diffused transistors require three diffusions and one epitaxial layer in the proposed process. Since no isolation or reachthrough diffusions are involved, this technique could reduce the area of a memory or logic cell by 50% or more. 430 M. B. VORA IntroductionSince the advent of planar silicon technology and its application in the fabrication of npn bipolar transistors, several integration schemes have been proposed. The most critical processing steps in planar technology are the diffusion of impurities into silicon at high temperature, the epitaxial vapor growth of a single-crystal silicon layer on a silicon substrate, and the selective etching of thermally grown oxide on silicon wafers with photoresists. The most commonly used structure, which utilizes epitaxy and diffusion to their fullest advantage, is shown in Fig. I. Typical dimensions are as indicated. The complete fabrication process, in brief, is as follows: On a p-substrate, an n" subcollector diffusion is made selectively, followed by an epitaxial growth of n-type silicon. The next step is to make p+ isolation diffusion to define n-type isolation pockets. Then, p+ base and n+ emitter diffusions are carried out. Finally, contact "windows" are opened through the insulation layer, and a metallic interconnection pattern is etched.The reverse-biased pn junction surrounding each n pocket isolates each bipolar transistor within it from the ones in other pockets. The buried n+ subcollector ensures low collector series resistance, and at the same time n epitaxy allows high collector-base breakdown voltage and low collector-base capacitance. The double-diffused p+ base region and n" emitter region ensure high emitter efficiency and good basewidth control, which in turn yields superior common emitter current gain (h FE ) and cut-off frequency (fT) characteristics.