A `Self-Body-Biased' SOI MOSFET: A Novel Body-Voltage-Controlled SOI MOSFET for Low Voltage Applications

Abstract

A new silicon-on-insulator metal-oxide-semiconductor field effect transistor (SOI MOSFET) structure utilizing a novel body potential control scheme is proposed and studied by simulation. In the 'ON' state its body potential is electrically isolated from the external body terminal by a gate depletion layer, and is controlled automatically through its drain current and drain voltage. More than 30% improvement in its current drivability over bulk counterparts is predicted. Mixed-mode simulation shows that a complementary MOS (CMOS) inverter composed of the proposed devices has a much shorter propagation delay than that in the case of a bulk CMOS inverter. Simulation results also reveal that there is no history effect in its propagation delay whereas a strong history effect exists in conventional floating-body counterparts. This is because the proposed device in the 'OFF' state is functionally equivalent to a body-tied partially-depleted SOI MOSFET, allowing excess majority carriers, which are the main cause of the 'history effect', to be swept away from the body terminal every time it goes to the 'OFF' state.

Feasibility Study of a Novel Four Transistor Silicon-on-Insulator Static Random Access Memory Cell Utilizing Partial Trench Isolation

“…One of the candidate device structures for such applications is the ''selfbody-biased'' (''SBB'') silicon-on-insulator (SOI) metaloxide-semiconductor field-effect transistor (MOSFET), which utilizes the expansion of the gate depletion layer beneath the auxiliary ''T-shaped'' gate electrode in order to modulate the body potential, thus enhancing its current drivability in the ''ON'' state. [1][2][3] By further modifying the gate electrode shape, the author has already proposed the ''SBB'' static random access memory (SRAM) cell operating at 0.5 V. 4,5) However this ''SBB'' SRAM cell has limited layout flexibility because it inevitably requires the ''Hshaped'' gate electrodes for realizing the cross-coupled inverter pair of the SRAM cell.…”