A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS

Zhang, Zhichao; Chen, Li; Djahanshahi, H.

doi:10.1109/ccece.2018.8447827

Cited by 7 publications

(10 citation statements)

References 6 publications

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“…A current of 4 mA feeds the controlled oscillator, and the post-layout simulated power consumption is 18 mW. In order to take control of the oscillation frequency, a couple of varactors are added at the output of each stage [ 21 , 22 ].…”

Section: Ring Oscillator Based On a Cascade Of Three Current Mode mentioning

confidence: 99%

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Monda

Ciarpi

Saponara

2020

Sensors

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This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

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Section: Ring Oscillator Based On a Cascade Of Three Current Mode mentioning

confidence: 99%

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Monda

Ciarpi

Saponara

2020

Sensors

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“…Its sizing considers that, according to Equation (1), the oscillation frequency is inversely proportional to both the number of CML stages N and the propagation delay τ. Therefore, to achieve a high oscillation frequency, the delay must be reduced [16,18]. It can be approximated by Equation (2), so that, varying the transistors dimensions [15,18,19], the delay can be reduced by augmenting g ds and reducing the equivalent capacitance, where C L could be the dominant one.…”

Section: Cmos Differential Stage With Passive Loadmentioning

confidence: 99%

“…On the one hand, VCOs can be implemented using LC-tank structures, which can tune transistors to operate at higher frequencies than ring oscillators, are relatively immune to power supply noise [14], and have outstanding phase noise and jitter performance [13]. On the other hand, designing VCOs in a ring topology is frequently a more attractive alternative because of its wider tuning range, small layout area, higher gain, low cost, robustness to variations, simplicity and scalability in deep nanoscale processes [15,16]. One challenge of VCOs based on ring topologies is reducing the deterministic jitter induced by power supply noise [14].…”

Section: Introductionmentioning

confidence: 99%

“…In this manner, the CMOS CML stage has a P-type MOS transistor as load, which operates in the triode region and its associated resistance is controlled by a voltage source V ctrl . The associated resistance of the active load is connected with a load capacitor in which both give rise to a time constant τ, so that varying V ctrl makes varying the oscillation frequency [16], and depending on the number of CML stages N, one can use Equation (1). Extending the oscillation frequency in a wider range that can be controlled by varying V ctrl , requires a good design methodology.…”

Section: Introductionmentioning

confidence: 99%

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Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

et al. 2019

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The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.

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“…As a result, RHBD techniques are preferred for hardening solution [8]. For example, it has been demonstrated that the current-mode logic (CML) circuit is used as one of the core building blocks of high-speed integrated-circuit (IC) applications such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), and frequency synthesizers [9,10]. Typical CML circuits consist of two main parts, the AC differential signal path and the DC current source, in which a current-mirror structure is commonly implemented [11,12].…”

Section: Introductionmentioning

confidence: 99%

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits

Sarker

Jung

Ildefonso

et al. 2020

Sensors

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It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time significantly decrease. In the present work, we demonstrate how radiation hardening by design (RHBD) techniques utilized in DC bias blocks only (current mirrors) can also improve the SET response in AC signal paths of switching circuits (e.g., current-mode logic, CML) without any additional hardening in those AC signal paths. Four CML circuits both with and without RHBD current mirrors were fabricated in 130 nm SiGe HBT technology. Two existing RHBD techniques were employed separately in the current mirrors of the CML circuits: (1) applying internal negative feedback and (2) adding a large capacitor in a sensitive node. In addition, these methods are also combined to analyze the overall SET performance. The single-event transients of the fabricated circuits were captured under the two-photon-absorption laser-induced single-event environment. The measurement data clearly show significant improvements in SET response in the AC signal paths of the CML circuits by using the two radiation hardening techniques applied only in DC current mirrors. The peak output transient current is notably reduced, and the settling time upon a laser strike is shortened significantly.

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A SEE Insensitive CML Voltage Controlled Oscillator in 65nm CMOS

Cited by 7 publications

References 6 publications

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits

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