A second-order extension of the edge-selection algorithm for a ΣΔ-DAC architecture insensitive to oversampling clock jitter

Lee, Eel-Wan

doi:10.1080/00207210110037259

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2005

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“…There are different system configurations for achieving this goal. The overall performances of the different configurations may be classified by the noise level at the output [5]. In this letter we will describe two configurations and develop some robusttools to help the designer to choose the best configuration with maximum SNR at the output.…”

Section: Introductionmentioning

confidence: 99%

Time jitter analysis of 1-bit sigma-delta synthesizer

Avi

Israel

2005

AEU - International Journal of Electronics and Communications

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Section: Introductionmentioning

confidence: 99%

Time jitter analysis of 1-bit sigma-delta synthesizer

Avi

Israel

2005

AEU - International Journal of Electronics and Communications

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Time jitter analysis of 1-bit sigma-delta synthesizer

Abu

Lupa

2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel

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In this work we will introduce a general analysis of time jitter in Sigma-Delta synthesizer. One of the practical applications of I-bit Sigma-Delta systems is a generation of high-resolution local oscillator (LO). LO signals in transmit / receive circuits are typically generated using synthesizers, direct-digital synthesis (DDS), etc. In order to generate LO signals, one may use a single-bit SigmaDelta technique to encode sine waves. Due to hardware constraints, Sigma-Delta output is generally injected into a frequency multiplier system in order to generate a high frequency LO signals. Today, direct generation o f high frequency sinewave using a clock with higher frequency i s possible. In this letter we will analyze these different techniques and develop some robust tools that will help us to create a practical way of computation to decide how to choose the best configuration under minimum degradation of Signal to Noise Ratio (SNR) at the output of the LO generator system.

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A second-order extension of the edge-selection algorithm for a ΣΔ-DAC architecture insensitive to oversampling clock jitter

Cited by 2 publications

References 7 publications

Time jitter analysis of 1-bit sigma-delta synthesizer

Time jitter analysis of 1-bit sigma-delta synthesizer

Time jitter analysis of 1-bit sigma-delta synthesizer

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