A scalable neural chip with synaptic electronics using CMOS integrated memristors

Cruz-Albrecht, Jose; Derosier, Timothy; Srinivasa, Narayan

doi:10.1088/0957-4484/24/38/384011

Cited by 68 publications

(33 citation statements)

References 33 publications

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“…In [41], the authors used the stochastic nature of memristive devices (CBRAM) to design low-power processors for real-time auditory and visual pattern extraction applications. One particularly interesting recent advance has been the tape-out of a scalable neural chip design with recongurable front-end, analog processing core (90 nm CMOS) and memristor-based synaptic storage (16X8) consuming 130 mW for 576 nodes [42].…”

Section: Discussionmentioning

confidence: 99%

On designing circuit primitives for cortical processors with memristive hardware

Kudithipudi

Merkel

Ooi

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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Cortical processors, inspired by the neocortex, offer a promising paradigm to build the next generation of massively parallel, energy efficient, real-time information processing systems. Efforts in realizing a scalable cortical processor in hardware are hindered by stringent design requirements, including high degrees of connectivity, dense weight storage, robustness to variability, and complex hierarchical structures. Emerging memristive devices are proven to be effective in emulating the plasticity characteristics of the neocortex, including synaptic and non-synaptic plasticity, within a single device.In this paper, we review various approaches in designing and realizing memristive hardware primitives for cortical processors such as neurons, synapses, training functions. Scalability and associated challenges for large-scale network realization are also reviewed. Further, we discuss the application space of such processors.

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Section: Discussionmentioning

confidence: 99%

On designing circuit primitives for cortical processors with memristive hardware

Kudithipudi

Merkel

Ooi

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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“…The resulting analog neuromorphic chips emulate biological neurons by means of electric currents and voltages. Compared to the digital designs from the next subsection, these silicon neurons (Cruz-Albrecht, Derosier, & Srinivasa, 2013) enable continuous state updates without discretization errors. By leveraging the inherent dynamics of their analog building blocks for computation, they allow for a higher integration density than digital chips (Renaud et al, 2007).…”

Section: Analog Neuromorphic Chipsmentioning

confidence: 99%

“…In addition to the memristors, the nodes of the HRL architecture also contain auxiliary CMOS memory for storing synaptic weights which can be used to operate the chip without the memristors. Additional memory further allows for the adjustment of various neural parameters and time constants (Cruz-Albrecht et al, 2013).…”

Section: The Hrl Synapse Projectmentioning

confidence: 99%

“…Since the mapping of synapses changes in every STM time slot, the routing configuration of the nodes must be adapted correspondingly. For this reason, every node contains a connection memory which stores the configuration of a set of switches that control the routing along the axonal data lanes (Cruz-Albrecht et al, 2013). At the beginning of a new time slot, the states of these switches are adapted according to the corresponding entry of the connection memory.…”

Section: The Hrl Synapse Projectmentioning

confidence: 99%

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Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks

2015

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a b s t r a c tThe application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks.

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“…This variability can be caused by circuits mismatch, communication delays that affect the asynchronous communication, or the presence of faulty elements in the system. Thus, it is important to have control on the placement of neurons onto the hardware, which often involves dedicated algorithms or neural network compilers (see for example Brüderle et al, 2011; Cruz-Albrecht et al, 2013; Navaridas et al, 2013). In PyNCS, the modeler has direct control on the desired placement by being able to directly select the addresses of the neurons composing the desired population, if needed.…”

Section: The Neuromorphic Setup As a Spike-event Transceivermentioning

confidence: 99%

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems

Neftci¹,

Sheik²,

Indiveri³

2014

Front. Neuroinform.

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Neuromorphic hardware offers an electronic substrate for the realization of asynchronous event-based sensory-motor systems and large-scale spiking neural network architectures. In order to characterize these systems, configure them, and carry out modeling experiments, it is often necessary to interface them to workstations. The software used for this purpose typically consists of a large monolithic block of code which is highly specific to the hardware setup used. While this approach can lead to highly integrated hardware/software systems, it hampers the development of modular and reconfigurable infrastructures thus preventing a rapid evolution of such systems. To alleviate this problem, we propose PyNCS, an open-source front-end for the definition of neural network models that is interfaced to the hardware through a set of Python Application Programming Interfaces (APIs). The design of PyNCS promotes modularity, portability and expandability and separates implementation from hardware description. The high-level front-end that comes with PyNCS includes tools to define neural network models as well as to create, monitor and analyze spiking data. Here we report the design philosophy behind the PyNCS framework and describe its implementation. We demonstrate its functionality with two representative case studies, one using an event-based neuromorphic vision sensor, and one using a set of multi-neuron devices for carrying out a cognitive decision-making task involving state-dependent computation. PyNCS, already applicable to a wide range of existing spike-based neuromorphic setups, will accelerate the development of hybrid software/hardware neuromorphic systems, thanks to its code flexibility. The code is open-source and available online at https://github.com/inincs/pyNCS.

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A scalable neural chip with synaptic electronics using CMOS integrated memristors

Cited by 68 publications

References 33 publications

On designing circuit primitives for cortical processors with memristive hardware

On designing circuit primitives for cortical processors with memristive hardware

Neuromorphic implementations of neurobiological learning algorithms for spiking neural networks

PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems

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