2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) 2012
DOI: 10.1109/vlsi-soc.2012.7332096
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A scalable model based RTL framework zamiaCAD for static analysis

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“…In our previous work [12] we have proposed an approach to automatic localization of design errors based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The localization approach has been integrated to a highly scalable zamiaCAD RTL design framework [11].…”
Section: Introductionmentioning
confidence: 99%
“…In our previous work [12] we have proposed an approach to automatic localization of design errors based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The localization approach has been integrated to a highly scalable zamiaCAD RTL design framework [11].…”
Section: Introductionmentioning
confidence: 99%