2013 Euromicro Conference on Digital System Design 2013
DOI: 10.1109/dsd.2013.82
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A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors

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Cited by 4 publications
(1 citation statement)
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“…Based on preliminary work it became obvious, that a centralized architecture for hardware enhanced RTM does not provide sufficient scalability for many-core [24]. The instantiation of a single hardware enhanced RTM provides the possibility to highly optimize the hardware module, however it still may become a performance bottleneck.…”
Section: Contributionmentioning
confidence: 99%
“…Based on preliminary work it became obvious, that a centralized architecture for hardware enhanced RTM does not provide sufficient scalability for many-core [24]. The instantiation of a single hardware enhanced RTM provides the possibility to highly optimize the hardware module, however it still may become a performance bottleneck.…”
Section: Contributionmentioning
confidence: 99%