2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2017
DOI: 10.1109/reconfig.2017.8279769
|View full text |Cite
|
Sign up to set email alerts
|

A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
11
0

Year Published

2018
2018
2022
2022

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 17 publications
(14 citation statements)
references
References 20 publications
0
11
0
Order By: Relevance
“…One example for the PM is presented in Algorithm 1, which requires r − 1 DBL and at most r − 1 ADD operations per PM, whereas the number of ADD operations varies with the key. We focus on the worst-case complexity because most implementations will try to balance the number of ADD operations in ordered to harden the calculation against timing attacks [32,33].…”
Section: Elliptic Curve Point Multiplication For Binary Keysmentioning
confidence: 99%
See 2 more Smart Citations
“…One example for the PM is presented in Algorithm 1, which requires r − 1 DBL and at most r − 1 ADD operations per PM, whereas the number of ADD operations varies with the key. We focus on the worst-case complexity because most implementations will try to balance the number of ADD operations in ordered to harden the calculation against timing attacks [32,33].…”
Section: Elliptic Curve Point Multiplication For Binary Keysmentioning
confidence: 99%
“…Consequently, an attacker can estimate the current bit of the secret key by observing the power consumption over time. To avoid TA and SPA attacks, many publications balance the number of applied point operations using additional dummy ADD operations [22,24,[31][32][33][34].…”
Section: Resistance Against Side-channel Attacksmentioning
confidence: 99%
See 1 more Smart Citation
“…With two parallel multipliers, we managed to reduce it to 6 clock cycles. Due to the special architecture of modular inversion to improve timing, calculating modular squaring as well as 2 2 th powering needs 2 clock cycles respectively and 2 5 th powering needs 3 clock cycles. Higher order powering operations are implemented by applying lower order powering units iteratively.…”
Section: Latency Calculationmentioning
confidence: 99%
“…However, among these applications, some of the time-critical applications such as network servers where millions of heterogeneous client devices need to be connected, the processing speed of identity authentication needs to be further improved. In recent years, several ECC processor designs over binary field Koblitz curve have been proposed to increase encryption speed [5]- [9]. Since point multiplication (PM) is the main and the most time-consuming iterative operation during the whole encryption process, most researches focus on exploiting novel hardware architectures to speed up the operation process.…”
Section: Introductionmentioning
confidence: 99%