A scalable dual mode arithmetic unit for public key cryptosystems

Crowe, F.; Daly, Alan J.; Marnane, William P.

doi:10.1109/itcc.2005.33

Cited by 31 publications

(9 citation statements)

References 17 publications

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“…Similarly to our architecture, the design from [4] is able to compute bit-lengths for ECC and RSA without reconfiguration. It features multiple ECC-cores, which can be interconnected to a bigger core for RSA.…”

Section: Implementation Resultsmentioning

confidence: 99%

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

Laue

Molter

Rieder

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.

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Section: Implementation Resultsmentioning

confidence: 99%

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

Laue

Molter

Rieder

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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“…For the field p, p large prime, configurable and dedicated ALUs for modular addition, subtraction and multiplication based on [11] were implemented. In this section we will look only at the architecture implementing configurable ALUs.…”

Section: B Rom Instruction Setmentioning

confidence: 99%

SPA resistant elliptic curve cryptosystem using addition chains

Byrne

Crowe

Marnane

et al. 2007

IJHPSA

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Abstract-There has been a lot of interest in recent years in the problems faced by cryptosystems due to side channel attacks. Algorithms for elliptic curve point scalar multiplication such as the double and add method are prone to such attacks. By making use of special addition chains, it is possible to implement a Simple Power Analysis(SPA) resistant cryptosystem. In this paper a reconfigurable architecture for a cryptographic processor is presented. A SPA resistant algorithm for point multiplication is implemented and is shown to be faster than the double-and-add method. Post place and route results for the processor are given.

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“…3, we compare proposed SWMM and hybrid GFAU with existing processor. In case [5], support variable key size (256 to 1024-bit), 44.91 MHz frequency, 5,267 slices area, a RSA and ECC operation dependently. Proposed processor support more variable key size (128 to 2048-bit for RSA and 113 to 571-bit for ECC) length, a efficient RSA and ECC operation independently.…”

Section: Measurements and Comparisonsmentioning

confidence: 99%

An efficient scalable and hybrid arithmetic unit for public key cryptographic applications

Kim

Heo

et al. 2007

IEICE Electron. Express

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Abstract:In this paper, we propose an efficient scalable and flexible arithmetic unit which executes word-based multiplication and squaring for RSA arithmetic and addition, multiplication and inversion in GF(2 m ) for Elliptic Curve Cryptography (ECC) arithmetic operation. The Scalable Word-based Montgomery Modular arithmetic unit (SWMM) can process RSA with modified Finely Integrated Operand Scanning (FIOS) Montgomery algorithm. Also, the proposed flexible hybrid Galois Field Arithmetic Unit (GFAU) is beneficial in costeffectively implementing ECC operation extensions. The proposed processor is synthesized by employing Synopsys Design Analyzer with a Hynix 0.25 standard cell library at the worst case of 2.3 V , 100 • C. The synthesis results show that the gate count of processor is below 60,000.

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A scalable dual mode arithmetic unit for public key cryptosystems

Cited by 31 publications

References 17 publications

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications

SPA resistant elliptic curve cryptosystem using addition chains

An efficient scalable and hybrid arithmetic unit for public key cryptographic applications

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