A scalable delay insensitive asynchronous NoC with adaptive routing

Alhussien, Abdulaziz; Wang, Chifeng; Bagherzadeh, Nader

doi:10.1109/ictel.2010.5478830

Cited by 13 publications

(12 citation statements)

References 12 publications

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“…The final DVFS accurately models timing aspects as well as worst power consumption. The GALS support implements two resynchronization schemes, handshake [17] and FIFO [18], allowing trading area and power consumption over performance penalties. Both the handshake and the FIFO resynchronizers allows to partition the design into multiple VFIs, even if the handshake one severely impacts the system performance, as discussed in Section 3.5 and Section 4.4.…”

Section: Novel Contributionmentioning

confidence: 99%

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Zoni

Terraneo

Fornaciari

2015

J Sign Process Syst

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Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and

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Section: Novel Contributionmentioning

confidence: 99%

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Zoni

Terraneo

Fornaciari

2015

J Sign Process Syst

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“…After the propagation delay, the req signal enters into a 2 flip-flop chain in the downstream router that is used to prevent metastability. The third flip-flip in the chain is used jointly with the req stable signal as a front detector, since our resynchronizer operates on fronts to increase throughput [Alhussien et al 2010]. The front detector asserts the data valid line, signaling that there is a valid flit on the link.…”

Section: Resynchronization Methodsmentioning

confidence: 99%

“…The handshake resynchronizer represents a low-cost and -performance solution with respect to the FIFO schema, mainly due to the absence of storage elements. Starting from the work in Alhussien et al [2010], the framework implements a 2-way handshake protocol which adds only two single bit-lines-request and acknowledge-to a network link. Note that the same circuit has to be implemented for the credit link.…”

Section: Resynchronization Methodsmentioning

confidence: 99%

“…The proposed framework supports exploration of different multicore design metrics, providing accurate models for the actuators. Different simulation frameworks have appeared in literature and [Alhussien et al 2010] and FIFO [Miro Panades and Greiner 2007], allowing to trade area and power consumption over performance penalties. The power gating support is introduced starting from SPICE-level simulations to equip the simulation flow with accurate timing and power sleep transistor models.…”

Section: Novel Contributionmentioning

confidence: 99%

“…Traditional very large-scale integrated (VLSI) designs require a totally balanced clock distribution network to ensure minimal clock skew between communication logic blocks. However, such networks can consume up to 30% of the overall chip power [Alhussien et al 2010]. NoCs naturally fit the GALS design paradigm by organizing groups of routers in different VFIs, where the size of each VFI is the knob to balance power and performance.…”

Section: Introductionmentioning

confidence: 99%

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Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

Zoni

Fornaciari

2015

J. Emerg. Technol. Comput. Syst.

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Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multicore revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly dynamic voltage frequency scaling (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (globally asynchronous locally synchronous) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.

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An Asynchronous 2D-Torus Network-on-Chip Using Adaptive Routing Algorithm

Yan

et al. 2016

Big Data Computing and Communications

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A scalable delay insensitive asynchronous NoC with adaptive routing

Cited by 13 publications

References 12 publications

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

An Asynchronous 2D-Torus Network-on-Chip Using Adaptive Routing Algorithm

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