A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain

Farahini, Nasim; Hemani, Ahmed; Lansner, Anders; Clermidy, Fabian; Svensson, Christer

doi:10.1109/aspdac.2014.6742953

Cited by 15 publications

(17 citation statements)

References 15 publications

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“…by introducing cache memory close to the CPU or by using general purpose GPUs, are not viable, if energy consumption is factored in [36]. We then described dedicated FPGA and full custom ASIC architectures that carefully balance the use of memory and information processing resources for implementing deep networks [42], [57], [40] or large-scale computational neuroscience models [67]. While these dedicated architectures, still based on frames or graded (non-spiking) neural network models, represent an improvement over CPU and GPU approaches, the event-based architectures described in Sections II-B1 and II-C improve access to cache memory structures even further, because of their better use of locality in both space and time.…”

Section: Discussionmentioning

confidence: 99%

“…However, these devices, developed to implement conventional logic architectures with small numbers of input (fan-in) and output (fan-out) ports, do not allow designers to make dramatic changes to the system's memory structure, leaving the von Neumann bottleneck problem largely unsolved. The next level of complexity in the quest of implementing brain-like neural information processing systems is to design custom ASICs using a standard digital design flow [67]. Further customization can be done by combining standard design digital design flow for the processing elements, and custom asynchronous routing circuits for the communication infrastructure.…”

Section: Large Scale Models Of Neural Systemsmentioning

confidence: 99%

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Memory and Information Processing in Neuromorphic Systems

2015

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Abstract-A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biologicallike models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.

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Section: Discussionmentioning

confidence: 99%

Section: Large Scale Models Of Neural Systemsmentioning

confidence: 99%

Memory and Information Processing in Neuromorphic Systems

2015

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“…• DRAM Power Model: Since DRAMs contribute significantly to the power consumption of today's systems [19,9], there is a need for accurate power modelling. For our framework we use DRAMPower [6,5], which uses either parameters from datasheets, estimated via DRAMSpec [25] or measurements to model DRAM power.…”

Section: Simulation Framework For Approx Drammentioning

confidence: 99%

Efficient reliability management in SoCs - an approximate DRAM perspective

Jung

Mathew

Weis

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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In today's computing systems Dynamic Random Access Memories (DRAMs) have a large influence on performance and contribute significantly to the total power consumption. Thus, recent research activities bring the idea of approximate DRAM into focus to save power and improve performance by lowering the refresh rate or disabling refresh completely. Hence, fast and accurate models are required for a thoroughly exploration of approximate DRAM for error resilient applications. In this paper we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error resilient applications.

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“…For instance, the authors of [4] show in a power breakdown of a recent smartphone that DRAM contributes around 17% to the total system power. Moreover, there are applications, such as the GreenWave computing platform [29], in which 49% of the total power consumption has to be attributed to DRAMs, and even 80% for a system that imitates the human cortex based on an Application Specific Integrated Circuit (ASIC), as shown in [13]. In fact, the energy consumed per bit for accessing off-chip DRAM is two to three orders of magnitude higher than the energy required for on-chip memory accesses [27].…”

Section: Introductionmentioning

confidence: 99%

Integrating DRAM power-down modes in gem5 and quantifying their impact

Jagtap

Jung

Elsasser

et al. 2017

Proceedings of the International Symposium on Memory Systems

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Across applications, DRAM is a significant contributor to the overall system power, with the DRAM access energy per bit up to three orders of magnitude higher compared to on-chip memory accesses. To improve the power efficiency, DRAM technology incorporates multiple power-down modes, each with different trade-offs between achievable power savings and performance impact due to entry and exit delay requirements. Accurate modeling of these low power modes and entry and exit control is crucial to analyze the tradeoffs across controller configurations and workloads with varied memory access characteristics. To address this, we integrate the power-down modes into the DRAM controller model in the opensource simulator gem5. This is the first publicly available full-system simulator with DRAM power-down modes, providing the research community a tool for DRAM power analysis for a breadth of use cases. We validate the power-down functionality with sweep tests, which trigger defined memory access characteristics. We further evaluate the model with real HPC workloads, illustrating the value of integrating low power functionality into a full system simulator

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A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain

Cited by 15 publications

References 15 publications

Memory and Information Processing in Neuromorphic Systems

Memory and Information Processing in Neuromorphic Systems

Efficient reliability management in SoCs - an approximate DRAM perspective

Integrating DRAM power-down modes in gem5 and quantifying their impact

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