A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m)

Fei, Caixian; Fang, Zhou; Wu, Ning; Feng, Guorui; Jin, Wen; Qin, Peiyao

doi:10.1109/icct50939.2020.9295940

Cited by 3 publications

(1 citation statement)

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“…Attacks have been proposed to manipulate the faulty results so they can pass PV process [7]. A number of structures for the error detection in finite field multiplier have been proposed [10,11,12,13,14,15], but the faults out of multiplier can not be detected. Besides, fault detection is not enough for the cryptosystems that need transient faults tolerance.…”

Section: Introductionmentioning

confidence: 99%

Highly efficient architecture of elliptic curve scalar multiplication with fault tolerance over GF(2<sup>m</sup>)

Fang

Fei

et al. 2021

IEICE Electron. Express

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In this paper, an efficient hardware architecture of scalar multiplication is proposed for elliptic curve cryptography. To reduce circuit area, we propose an elliptic curve operation unit architecture for Montgomery Ladder Algorithm in projective coordinates. The basic modular arithmetic circuit in elliptic curve group operation module is reused to realize coordinates transformation and y-coordinate recovery operation. Considering concurrent error-detecting and fault-tolerant, we improve the existing error detection scheme by reusing intermediate results and predicting fault. The simulation and DC synthesis results show that the scalar multiplication circuit designed according to the proposed architecture reduces the time cost of fault detection in single iteration to 1 clock cycle at 100% fault detection rate, and the efficiency is improved 96% than the existing literature.

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