A scalable architecture for modular multiplication based on montgomery's algorithm

Abstract

This paper presents a scalable architecture for the computation of modular multiplication, based on the Montgomery multiplication (MM) algorithm. A word-based version of MM is presented and used to explain the main concepts in the hardware design. The proposed multiplier is able to work with any precision of the input operands, limited only by memory or control constraints. Its architecture gives enough freedom to select the word size and the degree of parallelism to be used, according to the available area and/or desired performance. Design trade offs are analyzed in order to identify adequate hardware configurations for a given area or bandwidth requirement.

Design and Evaluation of Novel Effective Montgomery Modular Multiplication Architecture

“…Therefore, this modular multiplication algorithm is timeconsuming algorithm [11,17]. To further improve the performance of Montgomery modular multiplication algorithm, several computational techniques and hardware implementation have been proposed such as [7,9,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27 ]. One of the efficient modular multiplication algorithms is KPartition Montgomery Modular Multiplication (KPM3) algorithm [7].…”

“…Although hardware implementation of the binary Montgomery modular multiplication is simple, but it is time-consuming operation. To improve the performance of Montgomery modular multiplication algorithm and architecture, several hardware implementation method and computational techniques have been developed that can be categories into four groups: using high-radix technique [11][12][13][14][15][16][17], using systolic array architecture [18][19][20], using carry-save addition architecture [11,16,21,22,23], and using scalable architecture [9,12,24,25,26,27].…”

A high speed Montgomery processor of 256-bit on FPGA

“…In M. Kaihara et al [4] and M. Schramm et al [5], they present shift and add modular multiplication algorithm; In prime field ECC processors, carry free structure is necessary to avoid lengthy data paths caused by carry propagation. There has been redundant schemes applied to different designs, for example, Carry Save Arithmetic (CSA) or Redundant Signed Digits (RSD); There is a scalable word based structure proposed in Tenca and Koc [6]. In D. Harris et al [7], the authors present a scheme that used left shifted multiplication and modulus to replace intermediate result.…”

A New Modified CMM Modular Exponentiation Algorithm

“…Montgomery modular multiplication (M3) algorithm [7] is an efficient algorithm for modular multiplication because it avoids division by the modulus [8] [9].There are many research efforts in order to speed up the performance of the Montgomery modular multiplication algorithm such as high-radix design [10][11] [12], scalable design [8][11] [12], parallel calculation quotient and partial result [3] and signed-digit recoding [9][13] [14].…”