A scalable and adaptable hardware NoC-based self organizing map

Abadi, Mehdi; Jovanovic, Slavisa; Khalifa, Khaled Ben; Weber, S.; Bedoui, Mohamed Hédi

doi:10.1016/j.micpro.2017.12.007

Cited by 21 publications

(21 citation statements)

References 11 publications

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“…From the results of Table 4, it should be noted that the SSOM hardware architecture is relatively competitive compared to other more recent architectures. In addition, unlike parallel SOM architectures [8, 17, 18], SSOM is adaptive, based on the sequencing of the specific SOM operations. The latter will be performed concurrently in each neuroprocessor that will constitute the SOM network.…”

Section: Results Of Implementation Of Ssom Architecturementioning

confidence: 99%

“…Configurable hardware appears well adapted to obtain efficient and flexible neural network implementation. Several SOM implementations on FPGA supports have been proposed [11–18]. Indeed, Porrmann et al in [11] successfully implemented, on a Virtex FPGA support, a reconfigurable SIMD architecture of an SOM network formed by a processing element (PE).…”

Section: Introductionmentioning

confidence: 99%

“…For image compression, the authors in [17] successfully integrated a completely parallel SOM on an FPGA circuit using a shared comparator to exploit the parallelism between different neuroprocessors. In [18], the authors have proposed a new scalable and adaptable SOM network hardware architecture. The suggested architecture would permit dynamically modifying the SOM network pattern only by reconfiguring each neuron.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

Khalifa

Blaiech

Bedoui

2019

Computational Intelligence and Neuroscience

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In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.

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Section: Results Of Implementation Of Ssom Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

Khalifa

Blaiech

Bedoui

2019

Computational Intelligence and Neuroscience

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“…To the best of our knowledge, no work has been carried out to reduce the time required for each iteration. This can be partially explained by the highly parallel nature of the computations inside each iterations, in so far as when a fast real world implementation is required, parallel solutions are proposed, like the use of an FPGA substrate with each neuron having its own circuitry, as in [1] and in [6]. However, parallel solutions should not lead to a lack of effort in optimizing the algorithms, as the majority of SOM training is performed on CPU, and parallel hardware can be costly and difficult to program.…”

Section: Introductionmentioning

confidence: 99%

A Fast Algorithm to Find Best Matching Units in Self-Organizing Maps

Bernard

Hueber

Girau

2020

Artificial Neural Networks and Machine Learning – ICANN 2020

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Self-Organizing Maps (SOM) are well-known unsupervised neural networks able to perform vector quantization while mapping an underlying regular neighbourhood structure onto the codebook. They are used in a wide range of applications. As with most properly trained neural networks models, increasing the number of neurons in a SOM leads to better results or new emerging properties. Therefore highly efficient algorithms for learning and evaluation are key to improve the performance of such models. In this paper, we propose a faster alternative to compute the Winner Takes All component of SOM that scales better with a large number of neurons. We present our algorithm to find the so-called best matching unit (BMU) in a SOM, and we theoretically analyze its computational complexity. Statistical results on various synthetic and real-world datasets confirm this analysis and show an even more significant improvement in computing time with a minimal degradation of performance. With our method, we explore a new approach for optimizing SOM that can be combined with other optimization methods commonly used in these models for an even faster computation in both learning and recall phases.

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“…Abadi et al (2018). Todos os trabalhos apresentam algumas modificações no algoritmo de computação neural, em relação às execuções tradicionais em software, com o propósito de torná-lo adequado para uma implementação direta e eficiente no chip.Porém, constatou-se que tais modificações são frequentemente apresentadas na literatura sem que haja referência às premissas teóricas que fundamenta o modelo neural.…”

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Metodologias para desenvolvimento de mapas auto-organizáveis de Kohonen executados em FPGA.

Sousa¹,

Del-Moral-Hernandez²

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The last main contribution of the work is the characterization of the FPGA-based SOM. This evaluation is important because, although similar, the computing processes of neural models in hardware are not necessarily identical to the same processes implemented in software. Hence, this contribution can be described as the analysis of the impact of the implemented changes, regarding the FPGA-based SOM compared to traditional algorithms. The comparison was performed evaluating the measures of topographic and quantization errors for the outputs produced by both implementations. This work also generated medium impact contributions, which can be divided into two groups: empirical and theoretical. The first empirical contribution is the survey of SOM applications which can be made possible by hardware implementations. The papers presented in this survey are classified according to their research areasuch as Industry, Robotics and Medicineand, in general, they use SOM in applications that require computational speed or embedded processing. Therefore, the continuity of their developments is benefited by direct hardware implementations of the neural network. The other two empirical contributions are the applications employed for testing the circuits developed. The first application is related to the reception of telecommunications signals and aims to identify 16-QAM and 64-QAM symbols. These two modulation techniques are used in a variety of applications with mobility requirements, such as cell phones, digital TV on portable devices and Wi-Fi. The SOM is used to identify QAM distorted signals received with noise. This research work was published in the Springer Journal on Neural Computing and Applications: Sousa; Pires e Del-Moral-Hernandez (2017). The second is an image processing application and it aims to recognize human actions captured by video cameras. Autonomous image processing performed by FPGA chips inside video cameras can be used in different scenarios, such as automatic surveillance systems or remote assistance in public areas. This second application is also characterized by demanding high performance from the computing architectures. All the theoretical contributions with medium impact are related to the study of the properties of hardware circuits for implementing the SOM model. The first of these is the proposal of an FPGA-based neighborhood function. The aim of the proposal is to develop a computational function to be implemented on chip that enables an efficient

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A scalable and adaptable hardware NoC-based self organizing map

Cited by 21 publications

References 11 publications

A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network

A Fast Algorithm to Find Best Matching Units in Self-Organizing Maps

Metodologias para desenvolvimento de mapas auto-organizáveis de Kohonen executados em FPGA.

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