A SAT-Based Debugging Tool for State Machines and Sequence Diagrams

Abstract

Abstract. An effective way to model message exchange in complex settings is to use UML sequence diagrams in combination with state machine diagrams. A natural question that arises in this context is whether these two views are consistent, i.e., whether a desired or forbidden scenario modeled in the sequence diagram can be or cannot be executed by the state machines. In case of an inconsistency, a concrete communication trace of the state machines can give valuable information for debugging purposes on the model level. This trace either hints to a message in the sequence diagram where the communication between the state machines fails, or describes a concrete forbidden communication trace between the state machines. To detect and explain such inconsistencies, we propose a novel SAT-based formalization which can be solved automatically by an off-the-shelf SAT solver. To this end, we present the formal and technical foundations needed for the SAT-encoding, and an implementation inside the Eclipse Modeling Framework (EMF). We evaluate the effectiveness of our approach using grammar-based fuzzing.

Giving a Model-Based Testing Language a Formal Semantics via Partial MAX-SAT

“…Up to this point, fra(q, i, q ) has not been represented in terms of a firstorder logic formula. In CSP problems, framing axioms explicitly ensure that every variable change has a defined cause [14]. However, this would require us to establish an explicit cause-and-effect relationship between variable changes to ensure that each secondary action is directly or indirectly caused by the primary action.…”

Synthesis and Consistency Verification of UML Sequence Diagrams with Hierarchical Structure

“…Egyed [12] provided consistency rules for UML class, sequence, and state machine diagrams. Kaufmann et al [13] proposed a method to verify whether state machine diagrams can execute a desired or forbidden sce-nario modeled by a sequence diagram using SAT solver. Yokogawa et al [14] developed a method for inter-model consistency verification of a sequence diagram and state machine diagrams using the FDR model checker [15].…”