A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency

Abstract

Asymmetric multicore processors (AMPs) consist of cores executing the same ISA, but di↵ering in microarchitectural resources, performance, and power consumption. As the computational bottleneck of a workload shifts from one resource to the next, during its course of execution, reassigning it to the core where it runs most e ciently can improve the overall energy e ciency. Simulation studies show that the performance bottlenecks can shift frequently, often within a few thousands cycles. With frequent core hooping, the overhead of thread migration becomes significant. To mitigate this overhead, we propose a morphable core that can assume one of four possible configurations to address the dominant performance bottlenecks, while retaining the same cache and registers. This way the architectural state remains intact while the morphable core is reconfigured in resources and frequency. We then implement a runtime scheme to decide the best configuration to run on and switch configuration as necessary. Simulation results indicate that on the average, the proposed scheme results in performance/watt improvement of 41%.

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

“…Switching between only these extreme architectures does not cater to the demands of all applications. Srinivasan et al proposed a dynamic heterogeneous architecture that reconfigures among multiple CCMs, with different voltage and frequency [21]. It was shown that DVFS combined with resource scaling, provides improved performance/Watt when switching at fine granularity.…”

“…Prior works have performed AMP core sizing to relieve processor performance bottlenecks using design space exploration [3], [21]. They found that if there is only one core type, it would resemble an existing commercial super-scalar OOO core, where the core parameters are chosen to strike a balance between achieving sufficient ILP and the frequency.…”

“…In contrast, we consider a single core that dynamically morphs into four core configuration modes (CCMs), shown in Table I, as in [21]. As the objective of this work is to develop an online scheme to effectively assign threads to different core types to strike a balance between throughput/Watt and reliability, the CCMs in Table I are only representatives of how diverse the CCMs could be.…”