A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Kareem, Husam; Dunaev, Dmitriy

doi:10.1016/j.mejo.2023.106022

Cited by 7 publications

(2 citation statements)

References 19 publications

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“…At first, every step of every RO had a MUX, resulting in a programmable RO, subsequently an improved CRO-PUF design, MUX-based CRO-PUF have been put forth to expand the size of CRPs that are generated [202], hybrid logic gate CRO-PUF [204]. Utilizing strengths and weaknesses from prior works for secret-keybased applications in security, the RACRO-PUF architecture shows promise as it exhibits robustness against four ML methods and offers significant improvements in CRP size, hardware utilization, and performance metrics [203]. Regarding circuit density and the per-CRP bit, the hn-CRO PUF is more economical than conventional CRO PUF designs.…”

Section: B Physical Unclonable Functions(pufs)mentioning

confidence: 99%

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

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To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.

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Section: B Physical Unclonable Functions(pufs)mentioning

confidence: 99%

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

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“…The RO pair is constructed from a series of delay units (DUs) that are configured by the challenge. The counters count the number of oscillations in the ROs, and an arbiter compares the counters to produce the response [8] [9]. The initial NAND gate enables the RO and guarantees the fluctuation of the propagated signal.…”

Section: Introductionmentioning

confidence: 99%

Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

Abulibdeh,

Saleh,

Mohammad

et al. 2024

Preprint

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In the realm of Internet of Things (IoT) security, the Physical Unclonable Function (PUF) emerges as a viable solution for generating individualized secure keys. These keys play a vital role in authentication, chip protection, and supply chain security, serving as crucial safeguards for resource-constrained IoT devices. This work introduces Boosted Configurable Ring Oscillator PUF (BC-PUF), an area-efficient variant of CROPUF that suits resource-constrained IoT devices. Additionally, BC-PUF employs an absorbent approach for the intermediate responses to optimize the utilization of CMOS delay configurations. Moreover, BC-PUF mitigates the risk of Machine Learning (ML)-based modeling attacks. BC-PUF is a multi-bit response architecture that has been developed, analyzed, and evaluated across 50 FPGAs, from each dataset of 10K Challenge-Response Pairs (CRPs) is extracted. Experimental results report average values of 50.2%, 40.4%, 42%, 3.925%, and 83% for uniformity, diffuseness, uniqueness, reliability, and Shannon entropy, respectively. In comparison to state-of-the-art designs, the BC-PUF design achieves area reductions ranging from 15% to 96.7% across various architectures and implementations, along with a power reduction of 9.7%. Moreover, BC-PUF demonstrates resilience against ML-based attacks, achieving a prediction accuracy of 51%.

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Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

Gupta,

Sindal,

Neema

2024

Microelectronics Journal

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A robust architecture of ring oscillator PUF: Enhancing cryptographic security with configurability

Cited by 7 publications

References 19 publications

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique

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