A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations

Zhang, Sai; Huang, Kejie; Shen, Haibin

doi:10.1109/tcsi.2020.2971642

Cited by 36 publications

(20 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The MAC results can be parallel computed to improve the performance. In addition, the multi-states resistive cell can provide higher precision and density to the CIM architecture [61]. For instance, the resistance of RRAM cell can be changed continuously from KΩ to MΩ between HRS and LRS [62][63][64].…”

Section: Emerging Non-volatile Memory Solutions On Cim Architecturementioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

View full text Add to dashboard Cite

An artificial intelligence (AI) processor is a promising solution for energy-efficient data processing, including health monitoring and image/voice recognition. However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture. Recently, the memory-centric architecture has been revised to solve the data movement issue, where the memory is equipped with the compute-capable memory technique, namely, computing-in-memory (CIM). In this paper, we analyze the requirement of AI algorithms on the data movement and low power requirement of AI processors. In addition, we introduce the story of CIM and implementation methodologies of CIM architecture. Furthermore, we present several novel solutions beyond traditional analog-digital mixed static random-access memory (SRAM)-based CIM architecture. Finally, recent CIM tape-out studies are listed and discussed.

show abstract

Section: Emerging Non-volatile Memory Solutions On Cim Architecturementioning

confidence: 99%

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Chang

Zhang

et al. 2021

Sci. China Inf. Sci.

View full text Add to dashboard Cite

show abstract

“…They had previously used the same idea to construct a family of hybrid CMOS-memristive logic devices, so that the approach was compatible with existing CMOS logic [163]. In addition to the aforementioned achievements, a novel RRAM-based very long instruction word (VLIM) architecture for an in-memory computing (ReVAMP) system was also proposed [164]. Its data storage and computation memory (DCM) that performs data and in-memory computation makes use of RRAM crossbar memory, while the instruction memory (IM) stores the instruction and is accessed using the program counter (PC).…”

Section: Potential For Logic Operationsmentioning

confidence: 99%

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Xiong

et al. 2020

Materials

View full text Add to dashboard Cite

Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.

show abstract

“…The energy cost per DP for CM in Table III is obtained by substituting C = C BL and V o = ∆V BL in (21), and using (25) with…”

Section: Compute Memorymentioning

confidence: 99%

Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications

Gonugondla¹,

Sakr²,

Dbouk³

et al. 2020

Preprint

View full text Add to dashboard Cite

This paper obtains fundamental limits on the computational precision of in-memory computing architectures (IMCs). An IMC noise model and associated SNR metrics are defined and their interrelationships analyzed to show that the accuracy of IMCs is fundamentally limited by the compute SNR (SNRa) of its analog core, and that activation, weight and output precision needs to be assigned appropriately for the final output SNR SNRT → SNRa. The minimum precision criterion (MPC) is proposed to minimize the ADC precision. Three in-memory compute models -charge summing (QS), current summing (IS) and charge redistribution (QR) -are shown to underlie most known IMCs. Noise, energy and delay expressions for the compute models are developed and employed to derive expressions for the SNR, ADC precision, energy, and latency of IMCs. The compute SNR expressions are validated via Monte Carlo simulations in a 65 nm CMOS process. For a 512 row SRAM array, it is shown that: 1) IMCs have an upper bound on their maximum achievable SNRa due to constraints on energy, area and voltage swing, and this upper bound reduces with technology scaling for QS-based architectures; 2) MPC enables SNRT → SNRa to be realized with minimal ADC precision; 3) QS-based (QR-based) architectures are preferred for low (high) compute SNR scenarios.

show abstract

A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations

Cited by 36 publications

References 40 publications

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory

Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications

Contact Info

Product

Resources

About