A RISC architecture for symbolic computation

Abstract

The G-machine is a language-directed processor architecture designed to support graph reduction as a model of computation. It can carry out lazy evaluation of functional language programs and can evaluate programs in which logical variables are used. To support these language features, the abstract machine requires tagged memory and executes some rather complex instructions, such as to evaluate a function application.This paper explores an implementation of the G-machine as a high performance RISC architecture. Complex instructions can be represented by RISC code without experiencing a large expansion of code volume. The instruction pipeline is discussed in some detail. The processor is intended to be integrated into a standard, 32-bit memory architecture. Tagged memory is supported by aggregating data with tags in a cache.

Implementing lazy functional languages on stock hardware: the Spineless Tagless G-machine

“…Generally the discussion of this work has been focussed around the design of a so-called \abstract machine", which distils the key aspects of the compilation technique without becoming swamped in the details of source language or code generation. Quite a few such abstract-machine designs have been presented in recent years; examples include the Gmachine (Augustsson 1987]; Johnsson 1987]), TIM (Fairbairn & Wray 1987]), the Spineless G-machine (Burn, Peyton Jones & Robson 1988]), the Oregon G-machine chip (Kieburtz 1987]), the CASE machine (Davie & McNally 1989]), the HDG machine (Kingdon, Lester & Burn 1991]), the h ; Gi machine (Augustsson & Johnsson 1989]), and the ABC machine (Koopman 1990]). Early implementations, especially those based on graph reduction, were radically di erent from conventional compiler technology: the di erence between an SK combinator implementation (Turner 1979]) and (say) a Lisp compiler is substantial.…”