2006
DOI: 10.1080/00207540600596874
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A review of yield modelling techniques for semiconductor manufacturing

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Cited by 89 publications
(29 citation statements)
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“…The VDS model suggest that the bonding is caused by a point-like sources with a density of 0.9 mm −2 . These models and the other common yield models, 28,29,30 however, predict much higher probabilities than observed when the recess area is smaller than 1.5 mm 2 . This discrepancy is even higher with deeper recesses and the standard SC1 cleaning.…”
Section: Effect Of Temperature and Dilution Of Sc1 On Fusion Bonding-mentioning
confidence: 76%
“…The VDS model suggest that the bonding is caused by a point-like sources with a density of 0.9 mm −2 . These models and the other common yield models, 28,29,30 however, predict much higher probabilities than observed when the recess area is smaller than 1.5 mm 2 . This discrepancy is even higher with deeper recesses and the standard SC1 cleaning.…”
Section: Effect Of Temperature and Dilution Of Sc1 On Fusion Bonding-mentioning
confidence: 76%
“…These models can be validated by testing their prediction errors and comparing them with other yield models. Several published yield models are described in [10,11] and are summarized in Table I. Stapper and Rosner [35] suggest that a value of = 2 for the negative binomial model gave the best results in their work over a 16-year period, so = 2 was used in computing the negative binomial predicted values in these comparisons.…”
Section: Die-level Model Validationmentioning
confidence: 99%
“…Many of these models are described in [11,25] and are briefly shown in Table I. In these models, the variables used are defined as follows: D 0 = defects per area D i = defects per area from process step i A = area of a die A w = area of a wafer n = number of processing steps = clustering parameter…”
Section: Modeling Approachesmentioning
confidence: 99%
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“…With the reduction in device sizes, re-entrant flows (repetition of similar processing steps), and the variety of products to be manufactured, the complexity has strongly increased these recent years. This complexity, combined with the strong competition, forces semiconductor manufacturers to introduce several layers of controls in order to guarantee high yield [1]. Therefore, after some process steps, control operations are introduced at different levels (product, process, and equipment) in order to verify that the process is still under control and the product within specifications.…”
Section: Introductionmentioning
confidence: 99%