A review of SNN implementation on FPGA

Phạm, Quốc Trung; Nguyen, Thu Quyen; Hoang, Phuong; Dang, Quang Hieu; Nguyen, Duc Minh; Nguyen, Huy H.

doi:10.1109/mapr53640.2021.9585245

Cited by 14 publications

(7 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The event-driven method is mostly used in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC). FPGA is an expensive and flexible chip with limited resources, which is suited for laboratory prototype validation and not for actual deployment (Pham et al, 2021 ). Some researchers have made ASIC for simulating SNN, such as DYNAPs (Moradi et al, 2018 ), TrueNorth (Akopyan et al, 2015 ), and Loihi (Davies et al, 2018 ), etc.…”

Section: Related Workmentioning

confidence: 99%

“…Spiking neural networks (SNNs) (Maass, 1997 ) have attracted increasing attention because of their characteristics, including preferable biological interpretability and low-power processing potential (Akopyan et al, 2015 ; Shen et al, 2016 ; Davies et al, 2018 ; Moradi et al, 2018 ; Pei et al, 2019 ; Li et al, 2021 ; Pham et al, 2021 ). Compared to traditional artificial neural networks (ANNs), SNNs increase the time dimension so that they naturally support information processing in the temporal domain.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

EvtSNN: Event-driven SNN simulator optimized by population and pre-filtering

Tao²

2022

Front. Neurosci.

View full text Add to dashboard Cite

Recently, spiking neural networks (SNNs) have been widely studied by researchers due to their biological interpretability and potential application of low power consumption. However, the traditional clock-driven simulators have the problem that the accuracy is limited by the time-step and the lateral inhibition failure. To address this issue, we introduce EvtSNN (Event SNN), a faster SNN event-driven simulator inspired by EDHA (Event-Driven High Accuracy). Two innovations are proposed to accelerate the calculation of event-driven neurons. Firstly, the intermediate results can be reused in population computing without repeated calculations. Secondly, unnecessary peak calculations will be skipped according to a condition. In the MNIST classification task, EvtSNN took 56 s to complete one epoch of unsupervised training and achieved 89.56% accuracy, while EDHA takes 642 s. In the benchmark experiments, the simulation speed of EvtSNN is 2.9–14.0 times that of EDHA under different network scales.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

EvtSNN: Event-driven SNN simulator optimized by population and pre-filtering

Tao²

2022

Front. Neurosci.

View full text Add to dashboard Cite

show abstract

“…On one side, dedicated massively parallel hardware systems like SpiNNaker [11], TrueNorth [12], Loihi [13], and Tianjic [14] represent the group of large digital ASIC platforms for large-scale simulations. On the other side, FPGAs stand as stellar candidates to perform as SNN accelerators [15] for implementations that need smaller sizes and low energy consumption, offering the possibility to design more flexible neuromorphic processors targeting applications on the edge. This is precisely where this work is focused on.…”

Section: Introductionmentioning

confidence: 99%

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

López-Asunción,

Ituero

2024

Electronics

View full text Add to dashboard Cite

Spiking neural networks (SNNs) promise to perform tasks currently performed by classical artificial neural networks (ANNs) faster, in smaller footprints, and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls for finely-tuned custom implementations to keep pushing towards more efficient systems. To that end, we examined the architectural design space for executing spiking neuron models on FPGA platforms, focusing on achieving ultra-low area and power consumption. This work presents an efficient clock-driven spiking neuron architecture used for the implementation of both fully-connected cores and 2D convolutional cores, which rely on deep pipelines for synaptic processing and distributed memory for weight and neuron states. With them, we developed an accelerator for an SNN version of the LeNet-5 network trained on the MNIST dataset. At around 5.5 slices/neuron and only 348 mW, it is able to use 33% less area and four times less power per neuron as current state-of-the-art implementations while keeping low simulation step times.

show abstract

“…Over the past few years, Field-Programmable Gate Array (FPGA) platforms have become increasingly popular for addressing the needs of large-scale neuromorphic applications. FPGA implementation offers rapid, accurate, compact, and flexible alternatives compared to ASIC [26][27][28].…”

Section: Introductionmentioning

confidence: 99%

SC-IZ: A Low-Cost Biologically Plausible Izhikevich Neuron for Large-Scale Neuromorphic Systems Using Stochastic Computing

Liu,

Xiao,

et al. 2024

Electronics

View full text Add to dashboard Cite

Neurons are crucial components of neural networks, but implementing biologically accurate neuron models in hardware is challenging due to their nonlinearity and time variance. This paper introduces the SC-IZ neuron model, a low-cost digital implementation of the Izhikevich neuron model designed for large-scale neuromorphic systems using stochastic computing (SC). Simulation results show that SC-IZ can reproduce the behaviors of the original Izhikevich neuron. The model is synthesized and implemented on an FPGA. Comparative analysis shows improved hardware efficiency; reduced resource utilization, which is a 56.25% reduction in slices, 57.61% reduction in Look-Up Table (LUT) usage, and a 58.80% reduction in Flip-Flop (FF) utilization; and a higher operating frequency compared to state-of-the-art Izhikevich implementation.

show abstract

A review of SNN implementation on FPGA

Cited by 14 publications

References 38 publications

EvtSNN: Event-driven SNN simulator optimized by population and pre-filtering

EvtSNN: Event-driven SNN simulator optimized by population and pre-filtering

Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures

SC-IZ: A Low-Cost Biologically Plausible Izhikevich Neuron for Large-Scale Neuromorphic Systems Using Stochastic Computing

Contact Info

Product

Resources

About