A Review of Reliability in Gate-All-Around Nanosheet Devices

Abstract

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling.

Displacement Damage, Total Ionizing Dose, and Transient Ionization Effects in Gate-All-Around Field Effect Transistors

“…Specifically, there is a paradigm shift in GAA NSFET architecture which isolates both Source/Drain and the device channel from the substrate and the shallow trench isolation. This architecture is fundamentally different from current FinFET and schematically shown in Figure . Experimental evidence shows, that due to complete isolation of the device channel on all sides, GAA NSFETs have superior electrostatic performance compared to conventional FETs, leading to greater operational performance and lower power consumption …”

“…This architecture is fundamentally different from current FinFET and schematically shown in Figure 1. 9 Experimental evidence shows, that due to complete isolation of the device channel on all sides, GAA NSFETs have superior electrostatic performance compared to conventional FETs, leading to greater operational performance and lower power consumption. 2 Recent trends in the evolution of SOTA Complementary Metal-Oxide-Semiconductor (CMOS) have led to robust total ionizing dose (TID) and improved dose-rate upset (DRU) understanding of SOTA CMOS Integrated Circuits (IC)- s. 10−12 With the adoption of a new device geometry, the gate and isolation dielectric structure is fundamentally altered, with unknown impact on radiation performance.…”