A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

Ballo, Andrea; Bottaro, Michele; Grasso, Alfio Dario

doi:10.3390/app11062487

Cited by 35 publications

(32 citation statements)

References 49 publications

(86 reference statements)

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“…Interestingly, the most significant performance improvement was obtained with the CDN topology. Indeed, it was reported that with planar technology, this topology shows good VCE at the price of a reduced PCE with a 50 kΩ-load [6]. In our previous work, we already observed that the scaling from 90 nm to 32 nm was not so advantageous since the obtained VCE remained close to the one from the conventional CCDD topology for a PCE in the range of only 25-35%.…”

Section: Resultsmentioning

confidence: 71%

“…Indeed, a 50 Ω-antenna harvests an RF signal and transmits it to a rectifier by means of a matching impedance network [3,4]. Then, the rectifier or RF-DC converter provides a micropower DC signal to a Power Management Unit (PMU) to supply the chip (Figure 1) [5,6]. The most challenging step remains the rectifying stage that must produce DC with a low power supply.…”

Section: Introductionmentioning

confidence: 99%

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From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

et al. 2022

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In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

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Section: Resultsmentioning

confidence: 71%

Section: Introductionmentioning

confidence: 99%

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

et al. 2022

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“…An in‐depth review of power management integrated circuits has been published here. [ 141 ] Briefly, to further enhance the power harvesting capabilities of UPIs, electrical impedance matching can be employed. Impedance matching at a resonant frequency can be accomplished using an LC or shunt inductor or capacitor.…”

Section: Piezoelectric Ultrasound‐powered Implantsmentioning

confidence: 99%

Ultrasound‐Powered Implants: A Critical Review of Piezoelectric Material Selection and Applications

Turner

Senevirathne

Kilgour

et al. 2021

Adv Healthcare Materials

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Ultrasound‐powered implants (UPIs) represent cutting edge power sources for implantable medical devices (IMDs), as their powering strategy allows for extended functional lifetime, decreased size, increased implant depth, and improved biocompatibility. IMDs are limited by their reliance on batteries. While batteries proved a stable power supply, batteries feature relatively large sizes, limited life spans, and toxic material compositions. Accordingly, energy harvesting and wireless power transfer (WPT) strategies are attracting increasing attention by researchers as alternative reliable power sources. Piezoelectric energy scavenging has shown promise for low power applications. However, energy scavenging devices need be located near sources of movement, and the power stream may suffer from occasional interruptions. WPT overcomes such challenges by more stable, on‐demand power to IMDs. Among the various forms of WPT, ultrasound powering offers distinct advantages such as low tissue‐mediated attenuation, a higher approved safe dose (720 mW cm−2), and improved efficiency at smaller device sizes. This study presents and discusses the state‐of‐the‐art in UPIs by reviewing piezoelectric materials and harvesting devices including lead‐based inorganic, lead‐free inorganic, and organic polymers. A comparative discussion is also presented of the functional material properties, architecture, and performance metrics, together with an overview of the applications where UPIs are being deployed.

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“…Bootstrapped switches are widely used in many mixed-signal circuits [10][11][12][13]. For example, they are used in sample and hold circuits to achieve rail-to-rail switching functions [10,11], used in charge pump circuits to improve energy harvesting by node precharging [12,13], and so on. There are also reports on improving the performance of bootstrap switches [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

A BIST Scheme for Bootstrapped Switches

Tang

Tachibana

2021

Electronics

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This paper proposes a built-in self-test (BIST) scheme for detecting catastrophic faults in bootstrapped switches. The clock signal and the gate voltage of the sampling MOS transistor are taken as the observation signals in the proposed BIST scheme. Usually, the gate voltage of the sampling MOS transistor is greater than or equal to the supply voltage when the switch is turn on, and such a voltage is not suitable for observation. To solve this problem, a low power supply voltage is provided for the bootstrapped switch to obtain a suitable observation voltage. The proposed BIST scheme and the circuit under test (CUT) are realized with transistor level. The proposed BIST scheme was simulated by HSPICE. The simulated fault coverage is approximately 87.9% with 66 test circuits.

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A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

Cited by 35 publications

References 49 publications

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

Ultrasound‐Powered Implants: A Critical Review of Piezoelectric Material Selection and Applications

A BIST Scheme for Bootstrapped Switches

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