2006
DOI: 10.1016/j.mee.2006.01.162
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A review of line edge roughness and surface nanotexture resulting from patterning processes

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Cited by 75 publications
(54 citation statements)
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References 55 publications
(58 reference statements)
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“…Maintaining control of surface chemistry under conditions where low energy ion bombardment is required may necessitate novel surface and defect passivation schemes to prevent inadvertent changes in surface conditions. Control of plasma-induced surface roughness is another important challenge for processes where either smooth surfaces or controlled surface roughness are desired [55].…”
Section: Advances In Science and Technology To Meet Challengesmentioning
confidence: 99%
“…Maintaining control of surface chemistry under conditions where low energy ion bombardment is required may necessitate novel surface and defect passivation schemes to prevent inadvertent changes in surface conditions. Control of plasma-induced surface roughness is another important challenge for processes where either smooth surfaces or controlled surface roughness are desired [55].…”
Section: Advances In Science and Technology To Meet Challengesmentioning
confidence: 99%
“…7 Atomic-or nanometer-scale roughness on etched feature surfaces has also become an important issue to be resolved in the fabrication of nanoscale microelectronic devices, because the roughness formed during plasma etching would be comparable to the CD and the thickness of the layer being etched and/or the layer underlying. In gate fabrication, the roughness on feature sidewalls is responsible for the line edge roughness (LER) and line width roughness (LWR), 32,33 which cause the variability in gate or channel length and thus lead to that in transistor performance. 34,35 Moreover, in advanced three-dimensional (3D) device structures such as fin-type field effect transistors (FinFETs), 5,34,36 the effects of the fin as well as the gate LER and LWR become significant, 34 because LER and LWR occur also in the fin etch process, 5,36 and the conducting channel of FinFETs is formed on the top and sidewall surfaces of the fin.…”
Section: Introductionmentioning
confidence: 99%
“…[32][33][34][35][36] Sidewall roughening of the feature being etched is assumed to be caused by the pattern transfer of the mask edge roughness (resulting from lithography) into the underlayers being etched and also by that of grain boundaries of polycrystalline films to be etched into themselves. [32][33][34][35][36] In practice, the addition of depositive gas species such as CF 4 and/or reactive gases such as HBr giving depositive etch byproducts is often invoked to control and suppress the sidewall roughness in poly-Si gate and single-crystalline Si (c-Si) fin fabrication processes, 32,36 through etch inhibitor deposition or passivation layer formation on feature sidewalls. On the other hand, the sidewall roughness would also be caused by plasma-surface interactions themselves on feature sidewalls, where the ion incidence is assumed to be off normal or oblique to the surface being etched.…”
Section: Introductionmentioning
confidence: 99%
“…In fact for polymers plasma nanotexturing can simultaneously achieve optical transparency, antireflectivity and superhydrophobicity (1,9) . We would therefore like to emphasize that contrary to the undesirable effects of "grass" for nanoelectronics, controlled nanotexture formation may be valuable for nanomanufacturing of both large areas as well as devices, when one or more "smart" functionalities may be desired (10) . As the Greeks would say "there is no bad thing without a good side-effect", in other words one should not always cut the grass but rather control its growth.…”
Section: Introductionmentioning
confidence: 99%