A Retargetable Static Binary Translator for the ARM Architecture

Shen, Bor-Yeh; Hsu, Wei-Chung; Yang, Wuu

doi:10.1145/2629335

Cited by 21 publications

(7 citation statements)

References 37 publications

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“…Binary code lifting. LLBT [29,30] statically retargets binaries to different ISAs after lifting them to LLVM IR. MC-Semantics [16], Dagger [5] and RevNIC [10] (which is based on S 2 E) raise machine code for the purpose of high-level static binary translation on LLVM IR.…”

Section: Related Workmentioning

confidence: 99%

BinRec

Kroes

Altinay

Nash

et al. 2018

Proceedings of the 2018 Workshop on Forming an Ecosystem Around Software Transformation

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Compile-time specialization and feature pruning through static binary rewriting have been proposed repeatedly as techniques for reducing the attack surface of large programs, and for minimizing the trusted computing base. We propose a new approach to attack surface reduction: dynamic binary lifting and recompilation.We present BinRec, a binary recompilation framework that lifts binaries to a compiler-level intermediate representation (IR) to allow complex transformations on the captured code. After transformation, BinRec lowers the IR back to a "recovered" binary, which is semantically equivalent to the input binary, but has its unnecessary features removed. Unlike existing approaches, which are mostly based on static analysis and rewriting, our framework analyzes and lifts binaries dynamically. The crucial advantage is that we can not only observe the full program including all of its dependencies, but we can also determine which program features the end-user actually uses. We evaluate the correctness and performance of Bin-Rec, and show that our approach enables aggressive pruning of unwanted features in COTS binaries. CCS CONCEPTS• Security and privacy → Software and application security; Software reverse engineering;

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Section: Related Workmentioning

confidence: 99%

BinRec

Kroes

Altinay

Nash

et al. 2018

Proceedings of the 2018 Workshop on Forming an Ecosystem Around Software Transformation

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“…Static translation of indirect calls for OpenISA is a topic for future investigation, although Shen et al [32] already discussed solutions for full static translation of another RISC architecture, ARM. This translation employs a static binary translator.…”

Section: Emulation Engine: Direct Interpretation and Catsmentioning

confidence: 99%

“…Second, our current prototype does not handle indirect calls. Static translation of indirect calls for OpenISA is a topic for future investigation, although Shen et al already discussed solutions for full static translation of another RISC architecture, ARM. Therefore, we believe this problem is manageable.…”

Section: The Coisa Virtual Platformmentioning

confidence: 99%

Handling IoT platform heterogeneity with COISA, a compact OpenISA virtual platform

Auler

Millani

Brisighello

et al. 2016

Concurrency and Computation

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In face of the high number of different hardware platforms we need to program with Internet-of-Things (IoT), virtual machines (VMs) pose as a promising technology to allow a program once, deploy everywhere strategy. Unfortunately, existing VMs are either too heavy or use a stripped-down version to work on resource-constrained IoT devices. We present COISA, a compact virtual platform that relies on OpenISA, an instruction set architecture (ISA) that strives for easy emulation, to allow a single program to be deployed on many platforms, including tiny microcontrollers. By exploring the benefits of using a concrete ISA as our VM language, our experimental results indicate that COISA is easily portable and is capable of running unmodified guest applications in highly heterogeneous host platforms, including one with only 2 kB of RAM. For time-critical IoT applications on constrained platforms where extracting performance is of paramount importance, we propose the use of cloud-assisted translations, which employ static binary translation to deliver a binary fully converted to the native ISA used in the IoT device.HANDLING IOT PLATFORM HETEROGENEITY WITH COISA Our previous experience with ISA emulation and design [9,33,34] have shown us that a clean ISA, similar to MIPS, allows us to build a high-performance emulator capable of emulating guest

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“…再如, 翻译代码效率亦是二进制翻译的主要性能瓶颈. 已有研究基于 LLVM 优化引擎, 采用纯软件策略对翻译后代码进胡伟武等: 龙芯指令系统融合技术行优化, 如 HQEMU [16] 和 LLBT [17] . 此类方法无法解决体系结构差异导致的性能瓶颈, 如模拟 X86 EFLAG、模拟 ARM 条件存取指令等.…”

Section: 相关工作unclassified