A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications

Tan, Fei; Wang, Yiming; Yi-ming, Yang; Li, Liran; Zhang, Feng; Wang, Xinghua; Gao, Jianfeng; Liu, Yongpan

doi:10.1109/tcsii.2020.3013336

Cited by 18 publications

(7 citation statements)

References 8 publications

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“…As shown in Fig. 2 (b), 2T2R cells have been proposed to represent signed weights [14], [15]. In a 2T2R cell, the first memristor represents the positive portion of a weight and the second represents the negative portion.…”

Section: Background and Related Workmentioning

confidence: 99%

An Energy Efficient Time-Multiplexing Computing-in-Memory Architecture for Edge Intelligence

Xiao

Jiang

Chee

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The growing data volume and complexity of Deep Neural Networks (DNN) require new architectures to surpass the limitation of the von-Neumann bottleneck, with Computing-inmemory (CIM) as a promising direction for implementing energyefficient neural networks. However, CIM's peripheral sensing circuits are usually power and area hungry components. We propose a time-multiplexing Computing-in-Memory architecture (TM-CIM) based on memristive analog computing to share the peripheral circuits and process one column at a time. The memristor array is arranged in a column-wise manner that avoids wasting power/energy on unselected columns. In addition, DAC (digital-to-analog converter) power and energy efficiency, which turns out to be an even greater overhead than ADC (analog-to-digital converter), can be fine-tuned in TM-CIM for significant improvement. For a 256*256 crossbar array with a typical setting, TM-CIM saves 18.4× in energy with 0.136 pJ/MAC efficiency, and 19.9× area for 1T1R case and 15.9× for 2T2R case. Performance estimation on VGG-16 indicates that TM-CIM can save over 16× area. A trade-off between the chip area, peak power, and latency is also presented, with a proposed scheme to further reduce the latency on VGG-16, without significantly increasing chip area and peak power.

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Section: Background and Related Workmentioning

confidence: 99%

An Energy Efficient Time-Multiplexing Computing-in-Memory Architecture for Edge Intelligence

Xiao

Jiang

Chee

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…AIoT is the latest research topic among AI semiconductors [ 4 , 5 ]. Before the AIoT topic, a wide range of research has been conducted in implementing AI, that is, a neural network that mimics human neurons.…”

Section: Introductionmentioning

confidence: 99%

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors

Junaid

Arslan

Lee

et al. 2022

Sensors

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The convergence of artificial intelligence (AI) is one of the critical technologies in the recent fourth industrial revolution. The AIoT (Artificial Intelligence Internet of Things) is expected to be a solution that aids rapid and secure data processing. While the success of AIoT demanded low-power neural network processors, most of the recent research has been focused on accelerator designs only for inference. The growing interest in self-supervised and semi-supervised learning now calls for processors offloading the training process in addition to the inference process. Incorporating training with high accuracy goals requires the use of floating-point operators. The higher precision floating-point arithmetic architectures in neural networks tend to consume a large area and energy. Consequently, an energy-efficient/compact accelerator is required. The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device. The proposed accelerator engines have been verified on FPGA for both inference and training of the MNIST image dataset. The combination of 24-bit custom FP format with 16-bit Brain FP has achieved an accuracy of more than 93%. ASIC implementation of this optimized mixed-precision accelerator using TSMC 65nm reveals an active area of 1.036 × 1.036 mm2 and energy consumption of 4.445 µJ per training of one image. Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively. Therefore, the CNN structure using floating-point numbers with an optimized data path will significantly contribute to developing the AIoT field that requires a small area, low energy, and high accuracy.

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“…Garbage collectors are used in a variety of settings, including businesses, offices, schools, hospitals, and streets [1]. Waste management plays a crucial role in creating a clean environment in cities across the globe [2]. In an enclosed environment, garbage becomes an obstacle and a health hazard for residents because it can affect air quality and cleanliness.…”

Section: Introductionmentioning

confidence: 99%

Smart Garbage Bin Based on AIoT

Sung¹,

Devi²,

Hsiao³

et al. 2022

Intelligent Automation &Amp; Soft Computing

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Waste management and monitoring is a major concern in the context of the environment, and has a significant impact on human health. The concept of the Artificial Intelligence of Things (AIoT) can help people in everyday tasks in life. This study proposes a smart trash bin to help solve the problem of waste management and monitoring. Traditional methods of garbage disposal require human labor, and pose a hazard to the worker. The proposed smart garbage bin can move itself by using ultrasonic sensors and a web camera, which serves as its "eyes." Because the smart garbage bin is designed for indoor use and mobility, we use a Bluetooth beacon for location tracking, whereby the bin transmits a constant signal that the other devices in the environment can detect. A smart garbage bin was developed in this study to be used in the E315 research room in the Electrical Engineering Department of the National Chin-Yi University of Technology. An Android application was also developed to help users monitor waste in the smart bin.

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A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications

Cited by 18 publications

References 8 publications

An Energy Efficient Time-Multiplexing Computing-in-Memory Architecture for Edge Intelligence

An Energy Efficient Time-Multiplexing Computing-in-Memory Architecture for Edge Intelligence

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors

Smart Garbage Bin Based on AIoT

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