A reliable fault detection scheme for the AES hardware implementation

Bedoui, Mouna; Mestiri, Hassen; Bouallègue, Belgacem; Machhout, Mohsen

doi:10.1109/isivc.2016.7893960

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…Therefore, ( 5) is not valid in the complex model. However, because there exists a one-to-one correspondence between (x 1 , x 2 ) and (x 1 , x), and X 1 is independent of X , (5) can be modified to (8).…”

Section: A Amount Of Information Leakagementioning

confidence: 99%

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Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

2019

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The integrated circuits are faced with the threats of fault injection attacks (FIAs), which employ the faulty results and differential fault analysis to retrieve the vital information processed by the circuits. Countermeasures should be taken to protect the circuits against FIAs. This paper proposes a security evaluation method to quantitatively analyze the resistance of block ciphers with a Substitution-Permutation Network structure against FIAs from an information-theoretic perspective. A quantitative security factor is defined based on the amount of information leakage. Specifically, an extended cipher model is proposed to numerically analyze the theoretical amount of information leakage, and an efficient approach is proposed to obtain the actual amount of information leakage. Experiments by applying the quantitative evaluation method to AES circuit validate feasibility, efficiency and scalability of the method. The experimental results show that the security factor can quantify the effects of different fault models and countermeasures. 2000 fault injections are sufficient to complete the evaluation under the considered fault models within 10 microseconds. The proposed method can be used during the circuit design stage as well as chip testing stage.

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Section: A Amount Of Information Leakagementioning

confidence: 99%

“…The third kind is based on spatial redundancy [6], temporal redundancy [7] and information redundancy [8] to detect faults caused by FIA. The last kind is based on redundancy to correct faults [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

2019

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“…Two main types of countermeasures against timing FIAs have been proposed, sensorbased countermeasure [11,12] and information-based countermeasure [13,14]. Sensorbased countermeasures deploy analog/digital sensors, which are integrated into the target circuits, to detect the disturbance of the clock system.…”

Section: Introductionmentioning

confidence: 99%

“…[13] firstly implemented the parity check on the AES cipher circuit with the uniform grain, and [14] compared the performance of the parity code and the cyclic residue code for fault detection of the RC5 cipher circuit. As we know, the parity-code-based method fails when the number of the fault bits is even [11]. Therefore, for a higher fault coverage rate, the fine-grained parity code check is exploited but introduces higher overhead in hardware resource or power consumption [15].…”

Section: Introductionmentioning

confidence: 99%

Parity Check Based Fault Detection against Timing Fault Injection Attacks

Zhang

Wang

et al. 2022

Electronics

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Fault injection technologies can be utilized to steal secret information inside integrated circuits (ICs), and thus cause serious information security threats. Parity check has been adopted as an efficient method against fault injection attacks. However, the contradiction between security and overhead restricts the further development and applications of parity check in fault injection detection. This paper proposes two methods, mixed-grained parity check and word recombination parity check, based on parity check for the trade-off between security and overhead. The efficiency of the proposed approaches is verified on RC5, AES, and DES encryption implementations by clock glitch attack. Compared with the traditional parity check, the fault coverage rate of the mixed-grained approach can be increased by up to 53.69% by consuming 13.2% registers more. Against the traditional parity check, the fault coverage rate of the word recombination approach can be increased by up to 47.16% by using only 2.35% register more. The proposed approaches provide IC designers with countermeasure options targeting different design skills and design specifications.

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“…Various fault detection techniques have been introduced for different components of both classical and post-quantum cryptosystems, spanning both symmetric or asymmetric cryptography. For instance, [8] and [9] presented efficient fault detection schemes for the AES with very high error coverage, and, [10] and [11] proposed fault detection schemes for RSA.…”

Section: Introductionmentioning

confidence: 99%

Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA

Aghaie

Kermani

Azarderakhsh

2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Whether stemming from malicious intent or natural occurrences, faults and errors can significantly undermine the reliability of any architecture. In response to this challenge, fault detection assumes a pivotal role in ensuring the secure deployment of cryptosystems. Even when a cryptosystem boasts mathematical security, its practical implementation may remain susceptible to exploitation through side-channel attacks. In this paper, we propose a lightweight fault detection architecture tailored for modular exponentiation-a building block of numerous cryptographic applications spanning from classical cryptography to post quantum cryptography. Based on our simulation and implementation results on ARM Cortex-A72 processor, and AMD/Xilinx Zynq Ultrascale+, and Artix-7 FPGAs, our approach achieves an error detection rate close to 100%, all while introducing a modest computational overhead of approximately 7% and area overhead of less than 1% compared to the unprotected architecture. To the best of our knowledge, such an approach benchmarked on ARM processor and FPGA has not been proposed and assessed to date.

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A reliable fault detection scheme for the AES hardware implementation

Cited by 11 publications

References 6 publications

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks

Parity Check Based Fault Detection against Timing Fault Injection Attacks

Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA

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