A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Srivastava, Ankush; Singh, Virendra; Singh, A.D.; Saluja, Kewal K.

doi:10.1007/s10836-017-5692-7

Cited by 1 publication

(1 citation statement)

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“…7. Identifying the group of speed limiting paths is a challenging task in designing the system-on-chip (SoC), which in turn converts into a critical situation with the passing of time in stipulated design cycle time 14 . STA analysis is useful in identifying the paths with the help of widely implemented techniques.…”

Section: Related Work Andliterature Surveymentioning

confidence: 99%

Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

Rayudu*,

Jahagirdar,

Rao

2019

IJITEE

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FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

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Section: Related Work Andliterature Surveymentioning

confidence: 99%