A reconfigurable hardware architecture for the simulation of Rayleigh fading channels under arbitrary scattering conditions

Castillo, J. Vázquez; Vela-Garcia, L.; Gutiérrez, Carlos; Parra-Michel, R.

doi:10.1016/j.aeue.2014.07.008

Cited by 14 publications

(5 citation statements)

References 25 publications

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“…It should be pointed out that the maximum operating frequency is determined only by the frequency of DDS in this paper, not the frequency of this detector, which can be extended according to different applications. (1) 0.1 (1) 2 (1) 6.9/channel (1) Structure LDAC (2) LDAC (2) NLDAC (2) Hybrid (2) LDA (2) No. of Channel −59 (4) −58 (4) −55.1 −52 −59.9 (4) Power 0.7 W@ 1 GHz (5) 1.9 W@ 1 GHz (5) 0.13 W@ 2 GHz (5) 0.35 W@ 1.3 GHz (5) 0.6 W/channel @1 GHz (5) (1) Including pads.…”

Section: Measurement Results and Comparisonmentioning

confidence: 99%

“…of Channel −59 (4) −58 (4) −55.1 −52 −59.9 (4) Power 0.7 W@ 1 GHz (5) 1.9 W@ 1 GHz (5) 0.13 W@ 2 GHz (5) 0.35 W@ 1.3 GHz (5) 0.6 W/channel @1 GHz (5) (1) Including pads. (2) NLDAC, LDAC and Hybrid are the abbreviations of nonlinear DAC, linear DAC and hybrid DAC respectively. (3) Spectrum analyzer and other instruments are required.…”

Section: Measurement Results and Comparisonmentioning

confidence: 99%

“…−82 (1) /−81 (2) Detection time [µs] (3) 1 (1) Maximum operating frequency [MHz] 519 (1) /400 (2) (1) Simulation result. (2) Test result. (3) The time needed for one energy detection operation.…”

Section: Detection Accuracy [Dbm]mentioning

confidence: 99%

“…With the development of digital signal processing and integrated circuit technology, the direct digital frequency synthesizer (DDS) has become a popular solution for clock and signal generation, frequency modulation and test equipment [1,2]. Figure 1a shows the block diagram of a traditional DDS, in which the DDS core, that is composed of an N-bit phase accumulator and an angle-to-amplitude converter, is followed by a digital-to-analog converter (DAC).…”

Section: Introductionmentioning

confidence: 99%

“…These clocks and harmonic spurs modulate each other through substrate, power, and ground coupling to produce a series of frequency-determined spurs known as clock-induced-spurs, which are the most decisive factor for SFDR. The location of these spurs can be described in (2), where f o and f p are the output frequency and spurs' frequencies, respectively [10]. The authors in [9,10] present a method for adding auxiliary DDS blocks to reduce clock-induced-spurs for DDS.…”

Section: Introductionmentioning

confidence: 99%

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An Automatic Clock-Induced-Spurs Detector Based on Energy Detection for Direct Digital Frequency Synthesizer

Lei

Zhang

Deng

et al. 2022

Sensors

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A clock-induced-spurs detector, composed of a programmable low-pass filter (LPF), energy detector and spur detection algorithm, is presented and applied to a four-channel 1 gigabit-samples-per-second (GSPS) direct digital frequency synthesizer (DDS). The proposed detector realizes the detection of spurs based on energy-detection, and the spur detection algorithm is adopted to automatically extract the amplitude and phase of clock-induced spurs, generated by the intermodulation of harmonic spurs and multiple clocks. Finally, the extracted features are sent to auxiliary DDS to decrease the target spur, following which the detector can be turned off to save power. Additionally, the detected characteristics under different output conditions can be read out through the interface for rapid frequency switching. The proposed detector integrated into a DDS is fabricated with a 65 nm complementary metal oxide semiconductor (CMOS) process and has an area of 190 μm × 320 μm. The measured power consumption is roughly 38 mW, consuming 6% that of a single-channel DDS. The test results show that the spurious-free dynamic range (SFDR) of this DDS can be successfully enhanced from −43.1 dBc to roughly −59.9 dBc without any off-chip instruments. This effectively proves that the detection accuracy of this detector can reach around −81 dBm.

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