A Reconfigurable Gaussian/Triangular Basis Functions Computation Circuit

Abuelma'Ati, Muhammad Taher; Shwehneh, Abdullah

doi:10.1109/aiccsa.2006.205095

Cited by 3 publications

(4 citation statements)

References 21 publications

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“…Different hardware realizations of the Gaussian function have been proposed (Abuelma'ati & Shwehneh, 2006;Li et al, 2009;Masmoudi et al, 2002). The existing implementations usually involve analog circuits.…”

Section: Introductionmentioning

confidence: 99%

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

et al. 2012

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a b s t r a c tAn efficient transistor level implementation of a flexible, programmable Triangular Function (TF) that can be used as a Triangular Neighborhood Function (TNF) in ultra-low power, self-organizing maps (SOMs) realized as Application-Specific Integrated Circuit (ASIC) is presented. The proposed TNF block is a component of a larger neighborhood mechanism, whose role is to determine the distance between the winning neuron and all neighboring neurons. Detailed simulations carried out for the software model of such network show that the TNF forms a good approximation of the Gaussian Neighborhood Function (GNF), while being implemented in a much easier way in hardware. The overall mechanism is very fast.In the CMOS 0.18 µm technology, distances to all neighboring neurons are determined in parallel, within the time not exceeding 11 ns, for an example neighborhood range, R, of 15. The TNF blocks in particular neurons require another 6 ns to calculate the output values directly used in the adaptation process. This is also performed in parallel in all neurons. As a result, after determining the winning neuron, the entire map is ready for the adaptation after the time not exceeding 17 ns, even for large numbers of neurons. This feature allows for the realization of ultra low power SOMs, which are hundred times faster than similar SOMs realized on PC. The signal resolution at the output of the TNF block has a dominant impact on the overall energy consumption as well as the silicon area. Detailed system level simulations of the SOM show that even for low resolutions of 3 to 6 bits, the learning abilities of the SOM are not affected. The circuit performance has been verified by means of transistor level Hspice simulations carried out for different transistor models and different values of supply voltage and the environment temperature -a typical procedure completed in case of commercial chips that makes the obtained results reliable.

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Section: Introductionmentioning

confidence: 99%

A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip

et al. 2012

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“…If the high performances, low power consumption or low area occupancy are targeted, an ASIC is preferable to an FPGA implementation. There are some ASIC implementations of SOMs that we found in literature [3,4,5]. An ASIC implementation gives the best performances but is costly, demands high design efforts and has little or no flexibility.…”

Section: Related Workmentioning

confidence: 99%

“…Another important choice to take in HW SOM implementations is the type of neighbourhood function (NF) to use, whose function determines which neurons' coefficients in the vicinity of the winning one should be updated. In the original SOM algorithm, a Gaussian neighborhood function is used, but its hardware implementation demands complex arithmetic operations and is usually realized as an analog integrated circuit [4]. It is often approximated with other functions such as: rectangular, triangular, shift-register based [5] [7].…”

Section: Related Workmentioning

confidence: 99%

A Scalable Flexible SOM NoC-Based Hardware Architecture

Abadi

Jovanovic

Khalifa

et al. 2016

Advances in Self-Organizing Maps and Learning Vector Quantization

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In this paper, a parallel hardware implementation of a selforganizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a working frequency of 200MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.

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“…(1) Only one or two functions can be realized at a time; see for example [1] for a sine function generator realization, [3] where the realization of a Gaussian function generator is proposed, [7] for the inverse sine and the inverse cosine functions realizations, [8] for the realization of exponential and logarithmic functions, [10] where the realization of a tangent hyperbolic sigmoid is proposed, [13] where a triangular/trapezoidal function generator is presented, [14] where a sinh resistor is proposed for tanh linearization, [16] which presents a power law function generation, [17] where a Gaussian/triangular basis functions computation circuit is proposed, [19] for a fully differential tanh function realization, [23] which presents a realization for the hyperbolic tangent sigmoid function, [24] where radial basis function circuits are presented and [25] for the realization of an inverse sine function realization. (2) Recourse to the use of piecewise linear approximations to approximate the required nonlinear function; for example in [5,6,15,20,22], where piecewise linear approximations are used to approximate, and whence, realize several nonlinear functions.…”

Section: Introductionmentioning

confidence: 99%