1997
DOI: 10.1007/3-540-63465-7_244
|View full text |Cite
|
Sign up to set email alerts
|

A reconfigurable coprocessor for a PCI-based real time computer vision system

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

1998
1998
2007
2007

Publication Types

Select...
3
2

Relationship

0
5

Authors

Journals

citations
Cited by 8 publications
(1 citation statement)
references
References 8 publications
0
1
0
Order By: Relevance
“…Therefore, it is required a delay to store N-1 image lines (N being the row number of the convolution mask) that is implemented using N-1 FIFO memories. Lisa [10] offers a column-access architecture, which minimizes the amount of resources used in the FPGA by in-parallel processing the columns of pixels involved on each computation. Besides, by decomposing the mask weights in their binary representation, many multipliers can been replaced by shift-registers and adders.…”
Section: Hw Blocksmentioning
confidence: 99%
“…Therefore, it is required a delay to store N-1 image lines (N being the row number of the convolution mask) that is implemented using N-1 FIFO memories. Lisa [10] offers a column-access architecture, which minimizes the amount of resources used in the FPGA by in-parallel processing the columns of pixels involved on each computation. Besides, by decomposing the mask weights in their binary representation, many multipliers can been replaced by shift-registers and adders.…”
Section: Hw Blocksmentioning
confidence: 99%