A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Oliver, Neal; Sharma, Rahul; Chang, Stephen; Chitlur, Bhushan; Garcia, Elkin; Grecco, Joseph; Grier, Aaron; Ijih, Nelson; Liu, Yaping; Marolia, Pratik; Mitchel, Henry; Subhaschandra, Suchit; Sheiman, Arthur; Whisonant, Tim; Gupta, Prabhat K.

doi:10.1109/reconfig.2011.4

Cited by 48 publications

(31 citation statements)

References 9 publications

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“…Each port supports a link pair consisting of two uni-directional links that connect two processors; this supports traffic in both directions, simultaneously [27]. Additionally, the QPI comprises a cache coherency protocol to maintain the distributed memory and caches coherent during system operation [28].…”

Section: Interconnection Network On Multi-core Processorsmentioning

confidence: 99%

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

Park

2019

Mathematics

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This paper presents an efficient pipelined broadcasting algorithm with the inter-node transmission order change technique considering the communication status of processing nodes. The proposed method changes the transmission order for the broadcast operation based on the communication status of processing nodes. When a broadcast operation is received, a local bus checks the remaining pre-existing transmission data size of each processing node; it then transmits data according to the changed transmission order using the status information. Therefore, the synchronization time can be hidden for the remaining time, until the pre-existing data transmissions finish; as a result, the overall broadcast completion time is reduced. The simulation results indicated that the speed-up ratio of the proposed algorithm was up to 1.423, compared to that of the previous algorithm. To demonstrate physical implementation feasibility, the message passing engine (MPE) with the proposed broadcast algorithm was designed by using Verilog-HDL, which supports four processing nodes. The logic synthesis results with TSMC 0.18 µm process cell libraries show that the logic area of the proposed MPE is 2288.1 equivalent NAND gates, which is approximately 2.1% of the entire chip area. Therefore, performance improvement in multi-core processors is expected with a small hardware area overhead.

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Section: Interconnection Network On Multi-core Processorsmentioning

confidence: 99%

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

Park

2019

Mathematics

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“…The most recent of these works is a product from Intel, the QPI-based QuickAssist interface [18] [19]. QuickAssist manages both a coherence interface to an attached processor and the FPGA-local DRAM in-fabric, presenting a single processor-coherent memory interface to the FPGA.…”

Section: Related Workmentioning

confidence: 99%

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

Yang

Fleming

Adler

et al. 2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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Parallel programming has been widely used in many scientific and technical areas to solve large problems. While general-purpose processors have rich infrastructure to support parallel programming on shared memory, such as coherent caches and synchronization libraries, parallel programming infrastructure for FPGAs is limited. Thus, development of FPGAbased parallel algorithms remains difficult. In this work, we seek to simplify parallel programming on FPGAs. We provide a set of easy-to-use declarative primitives to maintain coherency and consistency of accesses to shared memory resources. We propose a shared-memory service that automatically manages coherent caches on multiple FPGAs. Experimental results of a 2-dimensional heat transfer equation show that the shared memory service with our distributed coherent caches outperforms a centralized cache by 2.6x. To handle synchronization, we provide new lock and barrier primitives that leverage native FPGA communication capabilities and outperform traditional through-memory primitives by 1.8x.

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“…(3) We evaluate the resulting system on a variety of platforms -PCIe connected FPGAs [33,46], cache coherent FPGAs [37], and Amazon F1 instances [7] -to explore deployments over the typical configurations made available by cloud providers. We also discuss in detail the effects of memory, computing, and I/O bandwidth on the resulting system.…”

Section: Introductionmentioning

confidence: 99%

Lowering the latency of data processing pipelines through FPGA based hardware acceleration

et al. 2019

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Web search engines often involve a complex pipeline of processing stages including computing, scoring, and ranking potential answers plus returning the sorted results. The latency of such pipelines can be improved by minimizing data movement, making stages faster, and merging stages. The throughput is determined by the stage with the smallest capacity and it can be improved by allocating enough parallel resources to each stage. In this paper we explore the possibility of employing hardware acceleration (an FPGA) as a way to improve the overall performance when computing answers to search queries. With a real use case as a baseline and motivation, we focus on accelerating the scoring function implemented as a decision tree ensemble, a common approach to scoring and classification in search systems. Our solution uses a novel decision tree ensemble implementation on an FPGA to: 1) increase the number of entries that can be scored per unit of time, and 2) provide a compact implementation that can be combined with previous stages. The resulting system, tested in Amazon F1 instances, significantly improves the quality of the search results and improves performance by two orders of magnitude over the existing CPU based solution.

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A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Cited by 48 publications

References 9 publications

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories

Lowering the latency of data processing pipelines through FPGA based hardware acceleration

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