A reconfigurable bidirectional active 2 dimensional dendrite model

Farquhar, E.; Abramson, David; Hasler, P.

doi:10.1109/iscas.2004.1328194

Cited by 16 publications

(10 citation statements)

References 6 publications

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“…Using channel model approaches, one can successfully build dense dendritic compartments and configurable structures (Farquhar et al, 2004) that compare well to classical models of dendrites (Nease et al, 2012). The resulting computation from dendritic elements is often debated, and in most computational models is ignored because of the increased computational complexity.…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…These implementations using fixed weights are not adaptable and hence can only be used in the recall phase. Adaptable analog synaptic weight techniques represent weights using variable conductance [76,77], voltage levels between floating gate CMOS transistors [71,[78][79][80], capacitive charges [81,82], or using charged coupled devices [83,84]. Some implementations use digital memories for more permanent weight storage [85].…”

Section: Analog Neural Hardware Implementationsmentioning

confidence: 99%

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Merchant

Peterson

2010

VLSI Design

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Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.

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“…A few systems have included the passive cable circuit model of the dendrite [9], specifically by implementing the dendritic resistance using switched-capacitor circuits [10], [11]. Some researchers have also incorporated active channels into VLSI dendritic compartments [12], [13], and showed their use for the propagation of dendritic spikes [13]. However, the impact of the synaptic input pattern on the functionality of neurons with a dendritic tree has not been investigated.…”

Section: Introductionmentioning

confidence: 99%

Input evoked nonlinearities in silicon dendritic circuits

Wang

Liu

2009

2009 IEEE International Symposium on Circuits and Systems

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Most VLSI spiking network implementations are constructed using point neurons. However, neurons with extended dendritic structures might offer additional computational advantages. Experimental evidence suggests that dendritic compartments could be considered as independent and parallel computational units. Depending on the synaptic input patterns, the dendritic integration could be either linear or nonlinear. We show the influence of spatio-temporal input patterns on the evoked dendritic integration in an aVLSI neuron chip with programmable dendritic compartments.Abstract-Most VLSI spiking network implementations are constructed using point neurons. However, neurons with extended dendritic structures might offer additional computational advantages. Experimental evidence suggests that dendritic compartments could be considered as independent and parallel computational units. Depending on the synaptic input patterns, the dendritic integration could be either linear or nonlinear. We show the influence of spatio-temporal input patterns on the evoked dendritic integration in an aVLSI neuron chip with programmable dendritic compartments.978-1-4244-3828-0/09/$25.00

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A reconfigurable bidirectional active 2 dimensional dendrite model

Cited by 16 publications

References 6 publications

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Input evoked nonlinearities in silicon dendritic circuits

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